rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL

Enable pinctrl for sdmmc and sdhci in SPL to support loading of FIT
image from SD and eMMC storage when booting from SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index a8c31fecafd85efdfcdff71fe21e830e6f179b34..f91740c1c0c8cca3242354eb3617409df745b599 100644 (file)
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -11,11 +11,67 @@
        };
 };
 
+&emmc_bus8 {
+       bootph-all;
+};
+
+&emmc_clk {
+       bootph-all;
+};
+
+&emmc_cmd {
+       bootph-all;
+};
+
+&emmc_datastrobe {
+       bootph-all;
+};
+
+&pinctrl {
+       bootph-all;
+};
+
+&pcfg_pull_none {
+       bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+       bootph-all;
+};
+
+&pcfg_pull_up {
+       bootph-all;
+};
+
+&sdmmc0_bus4 {
+       bootph-all;
+};
+
+&sdmmc0_clk {
+       bootph-all;
+};
+
+&sdmmc0_cmd {
+       bootph-all;
+};
+
+&sdmmc0_det {
+       bootph-all;
+};
+
+&sdmmc0_pwren {
+       bootph-all;
+};
+
 &sdhci {
        cap-mmc-highspeed;
        mmc-ddr-1_8v;
 };
 
+&uart2m0_xfer {
+       bootph-all;
+};
+
 &uart2 {
        clock-frequency = <24000000>;
        bootph-all;

diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index dfaacbc8839e671b93960a7c3f67fdbe4ff4dcce..dd1dd36a59b7a079908219b8c121467f25e08a94 100644 (file)
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_CLK=y
@@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y