riscv: cache: support cache enable in SPL stage

The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
index 39b0248c32342d93071b99a127e37b61453cf40f..d8fe1dfa95887d21af721033c0795d631325cff9 100644 (file)
--- a/arch/riscv/lib/sifive_cache.c
+++ b/arch/riscv/lib/sifive_cache.c
@@ -7,7 +7,10 @@
 #include <cpu_func.h>
 #include <log.h>
 #include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 
+#ifndef CONFIG_SPL_BUILD
 void enable_caches(void)
 {
        struct udevice *dev;
@@ -25,3 +28,21 @@ void enable_caches(void)
                        log_debug("ccache enable failed");
        }
 }
+#else
+static inline void probe_cache_device(struct driver *driver, struct udevice *dev)
+{
+       for (uclass_find_first_device(UCLASS_CACHE, &dev);
+            dev;
+            uclass_find_next_device(&dev)) {
+               if (dev->driver == driver)
+                       device_probe(dev);
+       }
+}
+
+void enable_caches(void)
+{
+       struct udevice *dev = NULL;
+
+       probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
+}
+#endif /* !CONFIG_SPL_BUILD */