ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments

The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
instruction which means "Invalidate Both Caches" when in fact the intent
is to clean and invalidate all caches.  So add an "mcr p15, 0, %0, c7,
c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
Both Caches" instruction to insure that memory is consistent with any
dirty cache lines.

Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
used.

Signed-off-by: George G. Davis <gdavis@mvista.com>

diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index ade7f4680077bd2f72892154abe7c7f85c2f5a93..2b9163173505aa5bae968ab8ed87bea682a85586 100644 (file)
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -71,6 +71,7 @@ static void cache_flush(void)
 {
        unsigned long i = 0;
 
+       asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
        asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
        asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
 }

diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 957f4389b2bf575087a4f1c4c2129dd61be787d9..922d01cb70080cd1605a801626b5a439796ee9f8 100644 (file)
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -226,8 +226,8 @@ cpu_init_crit:
         * flush v4 I/D caches
         */
        mov     r0, #0
-       mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
-       mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
+       mcr     p15, 0, r0, c7, c7, 0   /* Invalidate I+D+BTB caches */
+       mcr     p15, 0, r0, c8, c7, 0   /* Invalidate Unified TLB */
 
        /*
         * disable MMU stuff and caches