arm: mach-k3: Enable WA for R5F deadlock

On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
  cacheable write back/write allocate memory region and later
  on software execute barrier operation (DSB or DMB). R5F may
  hang at the barrier instruction.
2.When software is performing a mix of load and store operations
  within a tight loop and store operations are all writing to
  cacheable write back/write allocates memory regions, R5F may
  hang at one of the load instruction.

To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 99edcd9a247640e84e40ad0a621026e221bba5bb..a78ffbb674e37ca68cde812355b8fc578dc7e506 100644 (file)
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -82,6 +82,7 @@ void board_init_f(ulong dummy)
        ctrl_mmr_unlock();
 
 #ifdef CONFIG_CPU_V7R
+       disable_linefill_optimization();
        setup_k3_mpu_regions();
 #endif
 

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index bf631b74f841fdfd7a4f770375f1a718f9ab7759..50f5b81dfe5d2231727cf6628312ae70b5e7d8b8 100644 (file)
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -244,3 +244,28 @@ void board_prep_linux(bootm_headers_t *images)
                                       CONFIG_SYS_CACHELINE_SIZE));
 }
 #endif
+
+#ifdef CONFIG_CPU_V7R
+void disable_linefill_optimization(void)
+{
+       u32 actlr;
+
+       /*
+        * On K3 devices there are 2 conditions where R5F can deadlock:
+        * 1.When software is performing series of store operations to
+        *   cacheable write back/write allocate memory region and later
+        *   on software execute barrier operation (DSB or DMB). R5F may
+        *   hang at the barrier instruction.
+        * 2.When software is performing a mix of load and store operations
+        *   within a tight loop and store operations are all writing to
+        *   cacheable write back/write allocates memory regions, R5F may
+        *   hang at one of the load instruction.
+        *
+        * To avoid the above two conditions disable linefill optimization
+        * inside Cortex R5F.
+        */
+       asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
+       actlr |= (1 << 13); /* Set DLFO bit  */
+       asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
+}
+#endif

diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 8f9a023921b0d6079f6171e19d69ffcdc4089409..35d1609cdcde729234ffb9735d51d1f70cfcc180 100644 (file)
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -16,3 +16,4 @@
 
 void setup_k3_mpu_regions(void);
 int early_console_init(void);
+void disable_linefill_optimization(void);

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index d0bf86abeb222c078aacb075f2eeebc87da3b797..47587392661644727b49b18269784b03fe2b52cb 100644 (file)
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -87,6 +87,7 @@ void board_init_f(ulong dummy)
        ctrl_mmr_unlock();
 
 #ifdef CONFIG_CPU_V7R
+       disable_linefill_optimization();
        setup_k3_mpu_regions();
 #endif