powerpc/fsl-corenet: remove dead variant symbols

These are not supported as individual build targets, but instead
are supported by another target.

The dead p4040 defines in particular had bitrotted significantly.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 71b8bb7207e449b31c887b18fa1c15cec788bb20..33e93c88d727050e8c67381e7256f6c7467e9a97 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -62,7 +62,6 @@ COBJS-$(CONFIG_P1024) += ddr-gen3.o
 COBJS-$(CONFIG_P1025)  += ddr-gen3.o
 COBJS-$(CONFIG_P2010)  += ddr-gen3.o
 COBJS-$(CONFIG_P2020)  += ddr-gen3.o
-COBJS-$(CONFIG_PPC_P2040)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P2041)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)      += ddr-gen3.o
@@ -77,7 +76,6 @@ COBJS-$(CONFIG_PCI)   += pci.o
 COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
@@ -108,7 +106,6 @@ COBJS-$(CONFIG_P1024)       += p1021_serdes.o
 COBJS-$(CONFIG_P1025)  += p1021_serdes.o
 COBJS-$(CONFIG_P2010)  += p2020_serdes.o
 COBJS-$(CONFIG_P2020)  += p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7dd939589528b3d96ef05cde2f17670a7165b985..950ec2f485b7fe7b7d237d8d9da41ebc0fa028d7 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -306,30 +306,7 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
-#elif defined(CONFIG_PPC_P2040)
-#define CONFIG_MAX_CPUS                        4
-#define CONFIG_SYS_FSL_NUM_CC_PLLS     2
-#define CONFIG_SYS_FSL_NUM_LAWS                32
-#define CONFIG_SYS_FSL_SEC_COMPAT      4
-#define CONFIG_SYS_NUM_FMAN            1
-#define CONFIG_SYS_NUM_FM1_DTSEC       5
-#define CONFIG_NUM_DDR_CONTROLLERS     1
-#define CONFIG_SYS_FM_MURAM_SIZE       0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV       32
-#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-
-#elif defined(CONFIG_PPC_P2041)
+#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
 #define CONFIG_MAX_CPUS                        4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_NUM_LAWS                32
@@ -379,22 +356,7 @@
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 
-#elif defined(CONFIG_PPC_P4040)
-#define CONFIG_MAX_CPUS                        4
-#define CONFIG_SYS_FSL_NUM_CC_PLLS     4
-#define CONFIG_SYS_FSL_NUM_LAWS                32
-#define CONFIG_SYS_FSL_SEC_COMPAT      4
-#define CONFIG_SYS_FM_MURAM_SIZE       0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV       16
-#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,p4080-pcie"
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-
-#elif defined(CONFIG_PPC_P4080)
+#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_MAX_CPUS                        8
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     4
 #define CONFIG_SYS_FSL_NUM_LAWS                32
@@ -430,31 +392,7 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
-/* P5010 is single core version of P5020 */
-#elif defined(CONFIG_PPC_P5010)
-#define CONFIG_MAX_CPUS                        1
-#define CONFIG_SYS_FSL_NUM_CC_PLLS     2
-#define CONFIG_SYS_FSL_NUM_LAWS                32
-#define CONFIG_SYS_FSL_SEC_COMPAT      4
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_NUM_FMAN            1
-#define CONFIG_SYS_NUM_FM1_DTSEC       5
-#define CONFIG_SYS_NUM_FM1_10GEC       1
-#define CONFIG_NUM_DDR_CONTROLLERS     1
-#define CONFIG_SYS_FM_MURAM_SIZE       0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV       32
-#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-
-#elif defined(CONFIG_PPC_P5020)
+#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
 #define CONFIG_MAX_CPUS                        2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_NUM_LAWS                32

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 80101bb91be99863ba4d97cad4cda69fb900a817..c2d33b1d20bbaeabb75df9e5818770d6b94c9ca5 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1774,7 +1774,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2             0x00080000
 #define FSL_CORENET_RCWSR11_EC2_USB2                   0x00100000
 #endif
-#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
+#if defined(CONFIG_PPC_P2041) \
        || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII       0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII         0x00800000

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 9692575dc83017f8836c9e14c8bc3224f5a5a16c..cc573547557e037345bfd2a69e70955c320bec2e 100644 (file)
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -36,7 +36,6 @@ COBJS-y += tgec_phy.o
 COBJS-$(CONFIG_P1017)  += p1023.o
 COBJS-$(CONFIG_P1023)  += p1023.o
 # The P204x, P304x, and P5020 are the same
-COBJS-$(CONFIG_PPC_P2040) += p5020.o
 COBJS-$(CONFIG_PPC_P2041) += p5020.o
 COBJS-$(CONFIG_PPC_P3041) += p5020.o
 COBJS-$(CONFIG_PPC_P4080) += p4080.o

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index ce31fdc98db2a937b9f94824aea640a86aa343ed..31696655bbe242ade826348fd4dc51c6174eb135 100644 (file)
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -22,7 +22,7 @@
 
 /*
  * P2041 RDB board configuration file
- *
+ * Also supports P2040 RDB
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H

diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 4a2e47513d6015ed325c93cf2ed1796e507d1145..d6f2f5ceb8914a14bafda91cc2b50d86af16adeb 100644 (file)
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -22,6 +22,7 @@
 
 /*
  * P4080 DS board configuration file
+ * Also supports P4040 DS
  */
 #define CONFIG_P4080DS
 #define CONFIG_PHYS_64BIT

diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 4afc4f16ed1f90ad0a8598b8933c4a85ad23d6b9..8625f7629023b6ca49b49a456692a486df20eed8 100644 (file)
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -22,7 +22,7 @@
 
 /*
  * P5020 DS board configuration file
- *
+ * Also supports P5010 DS
  */
 #define CONFIG_P5020DS
 #define CONFIG_PHYS_64BIT