arm: mach-k3: Move disable_linefill_optimization() into R5 directory

The disable_linefill_optimization() function is only ever loaded by the
R5 core, move the code into the R5 directory.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index f411366778f0752baa4b460e854965717994d5a9..5d53efed85b1532eb7ebe7a816159897ed9e3322 100644 (file)
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -453,31 +453,6 @@ void board_prep_linux(struct bootm_headers *images)
 }
 #endif
 
-#ifdef CONFIG_CPU_V7R
-void disable_linefill_optimization(void)
-{
-       u32 actlr;
-
-       /*
-        * On K3 devices there are 2 conditions where R5F can deadlock:
-        * 1.When software is performing series of store operations to
-        *   cacheable write back/write allocate memory region and later
-        *   on software execute barrier operation (DSB or DMB). R5F may
-        *   hang at the barrier instruction.
-        * 2.When software is performing a mix of load and store operations
-        *   within a tight loop and store operations are all writing to
-        *   cacheable write back/write allocates memory regions, R5F may
-        *   hang at one of the load instruction.
-        *
-        * To avoid the above two conditions disable linefill optimization
-        * inside Cortex R5F.
-        */
-       asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
-       actlr |= (1 << 13); /* Set DLFO bit  */
-       asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
-}
-#endif
-
 static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions,
                               enum k3_firewall_region_type fwl_type)
 {

diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index b666ed34d10ef80700daab2e7c307801d325e799..ef0bf39d4503b3d977951a4adc8541d2bb991506 100644 (file)
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am62x/
 obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
 
+obj-y += common.o
 obj-y += lowlevel_init.o
 obj-y += r5_mpu.o
 

diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c
new file mode 100644 (file)
index 0000000..ef81f50
--- /dev/null
+++ b/arch/arm/mach-k3/r5/common.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * K3: R5 Common Architecture initialization
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/types.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+#include "../common.h"
+
+void disable_linefill_optimization(void)
+{
+       u32 actlr;
+
+       /*
+        * On K3 devices there are 2 conditions where R5F can deadlock:
+        * 1.When software is performing series of store operations to
+        *   cacheable write back/write allocate memory region and later
+        *   on software execute barrier operation (DSB or DMB). R5F may
+        *   hang at the barrier instruction.
+        * 2.When software is performing a mix of load and store operations
+        *   within a tight loop and store operations are all writing to
+        *   cacheable write back/write allocates memory regions, R5F may
+        *   hang at one of the load instruction.
+        *
+        * To avoid the above two conditions disable linefill optimization
+        * inside Cortex R5F.
+        */
+       asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
+       actlr |= (1 << 13); /* Set DLFO bit  */
+       asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
+}