mpc8610hpcd: Fix PCI mapping concepts

Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>

diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
index 2aad28aee1f0ba97819940eb0180122fc5782206..0fc83848472a5e025cd71f83b7dc54a33268dd07 100644 (file)
--- a/board/freescale/mpc8610hpcd/law.c
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -31,8 +31,8 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
        SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
 #endif
-       SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-       SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+       SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+       SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
        SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
        SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
        SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),

diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 2792778e320cae3a79b715b8e0bad95d01660540..a2097a5aff790bfc63ac6f79ccae1fe34bc100aa 100644 (file)
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -266,14 +266,14 @@ void pci_init_board(void)
 
                /* outbound memory */
                pci_set_region(r++,
-                        CONFIG_SYS_PCIE1_MEM_BASE,
+                        CONFIG_SYS_PCIE1_MEM_BUS,
                         CONFIG_SYS_PCIE1_MEM_PHYS,
                         CONFIG_SYS_PCIE1_MEM_SIZE,
                         PCI_REGION_MEM);
 
                /* outbound io */
                pci_set_region(r++,
-                        CONFIG_SYS_PCIE1_IO_BASE,
+                        CONFIG_SYS_PCIE1_IO_BUS,
                         CONFIG_SYS_PCIE1_IO_PHYS,
                         CONFIG_SYS_PCIE1_IO_SIZE,
                         PCI_REGION_IO);
@@ -321,14 +321,14 @@ void pci_init_board(void)
 
                /* outbound memory */
                pci_set_region(r++,
-                        CONFIG_SYS_PCIE2_MEM_BASE,
+                        CONFIG_SYS_PCIE2_MEM_BUS,
                         CONFIG_SYS_PCIE2_MEM_PHYS,
                         CONFIG_SYS_PCIE2_MEM_SIZE,
                         PCI_REGION_MEM);
 
                /* outbound io */
                pci_set_region(r++,
-                        CONFIG_SYS_PCIE2_IO_BASE,
+                        CONFIG_SYS_PCIE2_IO_BUS,
                         CONFIG_SYS_PCIE2_IO_PHYS,
                         CONFIG_SYS_PCIE2_IO_SIZE,
                         PCI_REGION_IO);
@@ -370,14 +370,14 @@ void pci_init_board(void)
 
                /* outbound memory */
                pci_set_region(r++,
-                        CONFIG_SYS_PCI1_MEM_BASE,
+                        CONFIG_SYS_PCI1_MEM_BUS,
                         CONFIG_SYS_PCI1_MEM_PHYS,
                         CONFIG_SYS_PCI1_MEM_SIZE,
                         PCI_REGION_MEM);
 
                /* outbound io */
                pci_set_region(r++,
-                        CONFIG_SYS_PCI1_IO_BASE,
+                        CONFIG_SYS_PCI1_IO_BUS,
                         CONFIG_SYS_PCI1_IO_PHYS,
                         CONFIG_SYS_PCI1_IO_SIZE,
                         PCI_REGION_IO);

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 27517e5b1fbe4f9c0a3355c94050bdc0fc2ea4fb..4bd3e0bd3d836247bd9b4cceaf3f98233b194b47 100644 (file)
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -273,11 +273,13 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS                0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe1000000
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
 /* For RTL8139 */
@@ -285,18 +287,18 @@
 #define _IO_BASE               0x00000000
 
 /* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE      0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe3000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00100000      /* 1M */
 
 /* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE      0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS       0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000      /* reuse mem LAW */
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe2000000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00100000      /* 1M */
 
@@ -364,7 +366,7 @@
 
 #define CONFIG_SYS_DBAT1L      (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
                        | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U      (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1U      (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT1L      (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT1U      CONFIG_SYS_DBAT1U
 
@@ -375,7 +377,7 @@
 
 #define CONFIG_SYS_DBAT2L      (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
                        | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U      (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2U      (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT2L      (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U      CONFIG_SYS_DBAT2U