board/ti/am335x: add support for beaglebone NOR Cape

This patch adds support of NOR cape[1] for both Beaglebone (white) and
Beaglebone(Black) boards. NOR Flash on this cape is connected to GPMC
chip-select[0] and accesses as external memory-mapped device.
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.

As GPMC chip-select[0] can be shared by multiple capes so NOR profile is
not enabled by default in boards.cfg. Following changes are required to
enable NOR cape detection when building am335x_boneblack board profile.

Signed-off-by: Tom Rini <trini@ti.com>

diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 439da4b969fbebabb7f19c2b076e3235d4d1f421..2a18ccbedefc3e731c575eafc317eb0fe487480d 100644 (file)
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
        {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},          /* BE_CLE */
        {-1},
 };
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
 static struct module_pin_mux bone_norcape_pin_mux[] = {
-       {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */
-       {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A1 */
-       {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A2 */
-       {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A3 */
-       {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A4 */
-       {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A5 */
-       {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A6 */
-       {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A7 */
-       {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A8 */
-       {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A9 */
-       {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE},       /* NOR_A10 */
-       {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
-       {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A12 */
-       {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A13 */
-       {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A14 */
-       {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A15 */
-       {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A16 */
-       {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A17 */
-       {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A18 */
-       {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A19 */
-       {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD0 */
-       {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD1 */
-       {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD2 */
-       {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD3 */
-       {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD4 */
-       {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD5 */
-       {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD6 */
-       {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD7 */
-       {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD8 */
-       {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD9 */
-       {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD10 */
-       {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD11 */
-       {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD12 */
-       {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD13 */
-       {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD14 */
-       {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD15 */
-
-       {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE},   /* NOR_CE */
-       {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
-       {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
-       {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
-       {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)},    /* NOR_WEN */
-       {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
+       {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS},                 /* NOR_A0 */
+       {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS},                 /* NOR_A1 */
+       {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS},                 /* NOR_A2 */
+       {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS},                 /* NOR_A3 */
+       {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS},                 /* NOR_A4 */
+       {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS},                 /* NOR_A5 */
+       {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS},                 /* NOR_A6 */
+       {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS},                 /* NOR_A7 */
+       {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD0 */
+       {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD1 */
+       {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD2 */
+       {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD3 */
+       {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD4 */
+       {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD5 */
+       {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD6 */
+       {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD7 */
+       {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD8 */
+       {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE},     /* NOR_AD9 */
+       {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE},    /* NOR_AD10 */
+       {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE},    /* NOR_AD11 */
+       {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE},    /* NOR_AD12 */
+       {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE},    /* NOR_AD13 */
+       {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE},    /* NOR_AD14 */
+       {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE},    /* NOR_AD15 */
+       {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN},     /* CE */
+       {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
+       {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
+       {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
+       {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN},    /* WEN */
+       {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
        {-1},
 };
 #endif
 
 #if defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux norboot_pin_mux[] = {
-       {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
-       {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
-       {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
-       {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
-       {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
-       {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
-       {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
-       {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
-       {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
-       {-1},
-};
-
 void enable_norboot_pin_mux(void)
 {
-       configure_module_pin_mux(norboot_pin_mux);
+       configure_module_pin_mux(bone_norcape_pin_mux);
 }
 #endif
 
@@ -349,7 +322,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                configure_module_pin_mux(mmc0_pin_mux);
 #if defined(CONFIG_NAND)
                configure_module_pin_mux(nand_pin_mux);
-#elif defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
                configure_module_pin_mux(bone_norcape_pin_mux);
 #else
                configure_module_pin_mux(mmc1_pin_mux);
@@ -393,6 +366,8 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                configure_module_pin_mux(mmc0_pin_mux);
 #if defined(CONFIG_NAND)
                configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR)
+               configure_module_pin_mux(bone_norcape_pin_mux);
 #else
                configure_module_pin_mux(mmc1_pin_mux);
 #endif

diff --git a/doc/README.cfi b/doc/README.cfi
index d087ff0d63e6615e17c240f707861dfd3a324821..81e7cf1d7e6617018c80129c4016c59eacc6c1f8 100644 (file)
--- a/doc/README.cfi
+++ b/doc/README.cfi
@@ -27,3 +27,16 @@ void flash_cmd_reset(flash_info_t *info)
 
 see also:
 http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
+
+
+Config Option
+
+  CONFIG_SYS_MAX_FLASH_SECT: Number of sectors available on Flash device
+
+  CONFIG_SYS_FLASH_CFI_WIDTH: Data-width of the flash device
+
+  CONFIG_CMD_FLASH: Enables Flash command library
+
+  CONFIG_FLASH_CFI_DRIVER: Enables CFI Flash driver
+
+  CONFIG_FLASH_CFI_MTD: Enables MTD frame work for NOR Flash devices