bool "Layerscape non-secure access support"
depends on ARCH_LS1021A || FSL_LSCH2
+config PCIE1
+ bool "PCIe controller #1"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE2
+ bool "PCIe controller #2"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE3
+ bool "PCIe controller #3"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE4
+ bool "PCIe controller #4"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
config FSL_USE_PCA9547_MUX
bool "Enable PCA9547 I2C Mux on Freescale boards"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
if TARGET_MPC8548CDS
+config PCI1
+ def_bool y
+
config SYS_BOARD
default "mpc8548cds"
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_TARGET_MPC8548CDS_LEGACY=y
+CONFIG_PCIE1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_TARGET_T1024RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_NXP_ESBC=y
CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_FSL_USE_PCA9547_MUX=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_FSL_QIXIS=y
+# CONFIG_QIXIS_I2C_ACCESS is not set
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
+<<<<<<< HEAD
+=======
+CONFIG_ENV_ADDR=0xFFE20000
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SRIO_PCIE_BOOT_SLAVE=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
+<<<<<<< HEAD
+=======
+CONFIG_ENV_ADDR=0xEFF20000
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_T2080RDB_REV_D=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+<<<<<<< HEAD
+=======
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
+CONFIG_PCIE4=y
+CONFIG_VID=y
+CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
+CONFIG_VOL_MONITOR_IR36021_READ=y
+CONFIG_VOL_MONITOR_IR36021_SET=y
+>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
# CONFIG_DEEP_SLEEP is not set
+CONFIG_PCIE1=y
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_IVM_BUS=2
CONFIG_MP=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_ADDR=0x401D0000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_ADDR=0x40300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_AHCI=y
# CONFIG_DEEP_SLEEP is not set
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_QSPI_BOOT=y
CONFIG_AHCI=y
# CONFIG_DEEP_SLEEP is not set
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_ENV_ADDR=0x40300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_ENV_ADDR=0x60500000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1043aqds_vdd_mv"
CONFIG_FSL_LS_PPA=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_FSL_LS_PPA=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_SPL=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_SPL=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_ENV_ADDR=0x40500000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_ENV_ADDR=0x60300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_ENV_ADDR=0x40300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_ENV_ADDR=0x60500000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="ls1046aqds_vdd_mv"
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_ENV_ADDR=0x40300000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_SPL=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_ENV_ADDR=0x40500000
CONFIG_AHCI=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
+CONFIG_PCIE1=y
+CONFIG_PCIE2=y
+CONFIG_PCIE3=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_PCI1 /* PCI controller 1 */
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#undef CONFIG_PCI2
-
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#ifndef __ASSEMBLY__
/* High Level Configuration Options */
#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-
/*
* PCI Windows
* Memory space is mapped 1-1, but I/O space must start from 0.
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_PCIE3
-#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_SRIO
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_PCIE3
-
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_PCIE3
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
* General PCIe
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
/*
* These can be toggled for performance analysis, otherwise use default.
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#include <linux/stringify.h>
-#define CONFIG_PCIE4
-
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
/* Environment in parallel NOR-Flash */
#define CONFIG_ENV_TOTAL_SIZE 0x040000
func(USB, usb, 0) \
func(DHCP, dhcp, na)
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS
#define __PHY_ETH2_MASK 0xFB
#define __PHY_ETH1_MASK 0xFD
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS
#define TSEC2_PHYIDX 0
#endif
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controler 1 */
-#define CONFIG_PCIE2 /* PCIE controler 2 */
-
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#ifdef CONFIG_PCI
#endif
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
#define FSL_QSPI_FLASH_NUM 2
/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 1
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
/* PCIe */
#ifndef SPL_NO_PCIE
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
/* I2C */
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.