arm, da850evm: Add an SPL for SPI boot

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>

diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 9c0eadea900c0150aa9d2d49a6f1efe3eee42c0e..9bd3e7146c435e884ed7ce4ed4f26cd50cb3506f 100644 (file)
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -108,7 +108,7 @@ static const struct pinmux_config gpio_pins[] = {
 #endif
 };
 
-static const struct pinmux_resource pinmuxes[] = {
+const struct pinmux_resource pinmuxes[] = {
 #ifdef CONFIG_DRIVER_TI_EMAC
        PINMUX_ITEM(emac_pins_mdio),
 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
@@ -135,6 +135,8 @@ static const struct pinmux_resource pinmuxes[] = {
        PINMUX_ITEM(gpio_pins),
 };
 
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
 static const struct lpsc_resource lpsc[] = {
        { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
        { DAVINCI_LPSC_SPI1 },  /* Serial Flash */

diff --git a/board/davinci/da8xxevm/u-boot-spl.lds b/board/davinci/da8xxevm/u-boot-spl.lds
new file mode 100644 (file)
index 0000000..6f6e065
--- /dev/null
+++ b/board/davinci/da8xxevm/u-boot-spl.lds
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+               LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text      :
+       {
+       __start = .;
+         arch/arm/cpu/arm926ejs/start.o        (.text)
+         *(.text*)
+       } >.sram
+
+       . = ALIGN(4);
+       .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+       . = ALIGN(4);
+       .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+       . = ALIGN(4);
+       .rel.dyn : {
+               __rel_dyn_start = .;
+               *(.rel*)
+               __rel_dyn_end = .;
+       } >.sram
+
+       .dynsym : {
+               __dynsym_start = .;
+               *(.dynsym)
+       } >.sram
+
+       .bss :
+       {
+               . = ALIGN(4);
+               __bss_start = .;
+               *(.bss*)
+               . = ALIGN(4);
+               __bss_end__ = .;
+       } >.sram
+
+       __image_copy_end = .;
+       _end = .;
+}

diff --git a/doc/README.davinci b/doc/README.davinci
index 5f1bdc836c437f8f10a02b669602cd31ba5db138..aa7c85011a377fe1e71690561d6ea28f88988a36 100644 (file)
--- a/doc/README.davinci
+++ b/doc/README.davinci
@@ -95,6 +95,15 @@ into the RAM.
 The programmers and UBL are always released as part of any standard TI
 software release associated with an SOC.
 
+Alternative boot method (DA850 EVM only):
+For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL)
+is provided to load U-Boot directly from SPI flash. In this case, the
+SPL does the low level initialization that is otherwise done by the SPL.
+To build U-Boot with this SPL, do
+make da850evm_config
+make u-boot.ais
+and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM.
+
 Environment Variables
 =====================
 

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 2e2aa19a45aec66ed01eac2a6614030c829e88dc..b30696af9fdf2b5b7e39006ba89c623d36dc1073 100644 (file)
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -65,6 +65,75 @@
 #define CONFIG_NR_DRAM_BANKS   1 /* we have 1 bank of DRAM */
 #define CONFIG_STACKSIZE       (256*1024) /* regular stack */
 
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (      \
+       DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
+       DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
+       DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
+       DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
+       DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+/*
+ * PLL configuration
+ */
+#define CONFIG_SYS_DV_CLKMODE          0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM     24
+#define CONFIG_SYS_DA850_PLL1_PLLM     21
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+                                       DV_DDR_PHY_EXT_STRBEN | \
+                                       (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (          \
+       (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
+       (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
+       (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
+       (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
+       (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
+       (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
+       (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (         \
+       (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
+       (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
+       (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
+       (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
+       (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
+       (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
+       (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
+       (0 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (                \
+       (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
+       (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
+       (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
+       (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
+       (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
+       (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
+       (0 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
+#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+
 /*
  * Serial Driver info
  */
@@ -76,6 +145,7 @@
 #define CONFIG_CONS_INDEX      1               /* use UART0 for console */
 #define CONFIG_BAUDRATE                115200          /* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
 
 #define CONFIG_SPI
 #define CONFIG_SPI_FLASH
@@ -242,6 +312,23 @@
 #undef CONFIG_CMD_ENV
 #endif
 
+/* defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LDSCRIPT    "$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK       0x8001ff00
+#define CONFIG_SPL_TEXT_BASE   0x80000000
+#define CONFIG_SPL_MAX_SIZE    32768
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x8000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE     0x30000
+
 /* additions for new relocation code, must added to all boards */
 #define CONFIG_SYS_SDRAM_BASE          0xc0000000
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \