powerpc/t2080qds: fix for 1000BASE-KX

1000BASE-KX(1G-KX) uses SGMII protocol but the serdes lane runs in 1G-KX
mode. By default, the lane runs in SGMII mode, when a MAC uses a lane
in 1G-KX mode, corresponding bit in PCCR1 for the lane needs to be set,
and needs to fixup dtb accordingly for kernel to do proper initialization.

Hwconfig "fsl_1gkx" is used to indicate a MAC runs in 1G-KX mode, FM1 MAC
1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
MAC runs in 1G-KX mode, set its' corresponding env in "fsl_1gkx",
'fm1_1g1' stands for FM1-MAC1, 'fm1_1g2' stands for FM1-MAC2, etc.

If all MAC 1/2/5/6/9/10 run in 1G-KX mode, the hwconfig should has below
setting:

fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: Fix compiling warning]
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
index e3eb5baf945742e45fcc075af80e3c55679ad3ff..83060c10f372d59e067083dbda96907918221afa 100755 (executable)
--- a/board/freescale/t208xqds/README
+++ b/board/freescale/t208xqds/README
@@ -104,6 +104,18 @@ XFI:
  set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
  XFI ports will use copper cable, the other two XFI ports will use fiber
  cable.
+1000BASE-KX(1G-KX):
+ - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
+ runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
+ in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
+ Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper
+ initialization.
+ Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
+ 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
+ MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
+ stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
+ For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
+ hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
 
 System Memory map
 ----------------

diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 8675dbb512e17886110385b9c79406cbdd077911..b82e9e7540208e49da8311805b563850d5b0e44d 100644 (file)
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -47,6 +47,15 @@
 #define EMI2           8
 #endif
 
+#define PCCR1_SGMIIA_KX_MASK           0x00008000
+#define PCCR1_SGMIIB_KX_MASK           0x00004000
+#define PCCR1_SGMIIC_KX_MASK           0x00002000
+#define PCCR1_SGMIID_KX_MASK           0x00001000
+#define PCCR1_SGMIIE_KX_MASK           0x00000800
+#define PCCR1_SGMIIF_KX_MASK           0x00000400
+#define PCCR1_SGMIIG_KX_MASK           0x00000200
+#define PCCR1_SGMIIH_KX_MASK           0x00000100
+
 static int mdio_mux[NUM_FM_PORTS];
 
 static const char * const mdio_names[] = {
@@ -195,6 +204,11 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
        int off;
 
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_T2080QDS
+       serdes_corenet_t *srds_regs =
+               (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+       u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
+#endif
        u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
                                FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 
@@ -205,9 +219,54 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
                switch (port) {
 #if defined(CONFIG_T2080QDS)
                case FM1_DTSEC1:
+                       if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(fdt, compat, addr,
+                                                  "phy_1gkx1");
+                               fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
+                               sprintf(buf, "%s%s%s", buf, "lane-c,",
+                                               (char *)lane_mode[0]);
+                               out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+                                        PCCR1_SGMIIH_KX_MASK);
+                               break;
+                       }
                case FM1_DTSEC2:
+                       if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(fdt, compat, addr,
+                                                  "phy_1gkx2");
+                               fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
+                               sprintf(buf, "%s%s%s", buf, "lane-d,",
+                                               (char *)lane_mode[0]);
+                               out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+                                        PCCR1_SGMIIG_KX_MASK);
+                               break;
+                       }
                case FM1_DTSEC9:
+                       if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(fdt, compat, addr,
+                                                  "phy_1gkx9");
+                               fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
+                               sprintf(buf, "%s%s%s", buf, "lane-a,",
+                                               (char *)lane_mode[0]);
+                               out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+                                        PCCR1_SGMIIE_KX_MASK);
+                               break;
+                       }
                case FM1_DTSEC10:
+                       if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(fdt, compat, addr,
+                                                  "phy_1gkx10");
+                               fdt_status_okay_by_alias(fdt,
+                                                        "1gkx_pcs_mdio10");
+                               sprintf(buf, "%s%s%s", buf, "lane-b,",
+                                               (char *)lane_mode[0]);
+                               out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+                                        PCCR1_SGMIIF_KX_MASK);
+                               break;
+                       }
                        if (mdio_mux[port] == EMI1_SLOT2) {
                                sprintf(alias, "phy_sgmii_s2_%x", phy);
                                fdt_set_phy_handle(fdt, compat, addr, alias);
@@ -219,7 +278,29 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
                        }
                        break;
                case FM1_DTSEC5:
+                       if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(fdt, compat, addr,
+                                                  "phy_1gkx5");
+                               fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
+                               sprintf(buf, "%s%s%s", buf, "lane-g,",
+                                               (char *)lane_mode[0]);
+                               out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+                                        PCCR1_SGMIIC_KX_MASK);
+                               break;
+                       }
                case FM1_DTSEC6:
+                       if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
+                               media_type = 1;
+                               fdt_set_phy_handle(fdt, compat, addr,
+                                                  "phy_1gkx6");
+                               fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
+                               sprintf(buf, "%s%s%s", buf, "lane-h,",
+                                               (char *)lane_mode[0]);
+                               out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+                                        PCCR1_SGMIID_KX_MASK);
+                               break;
+                       }
                        if (mdio_mux[port] == EMI1_SLOT1) {
                                sprintf(alias, "phy_sgmii_s1_%x", phy);
                                fdt_set_phy_handle(fdt, compat, addr, alias);
@@ -263,6 +344,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
                default:
                        break;
                }
+               if (media_type) {
+                       /* set property for 1000BASE-KX in dtb */
+                       off = fdt_node_offset_by_compat_reg(fdt,
+                                       "fsl,fman-memac-mdio", addr + 0x1000);
+                       fdt_setprop_string(fdt, off, "lane-instance", buf);
+               }
 
        } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
                switch (srds_s1) {