arm: socfpga: Move Stratix10 and Agilex clock manager common code

Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index f0b15f770cc5ed7d46e177ab5afe12afec79447d..be426a5cfb8fa51ae296c3cec45e55ee7a65fef9 100644 (file)
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -4,12 +4,13 @@
  */
 
 #include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
 #include <command.h>
 #include <init.h>
 #include <wait_bit.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/clock_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,6 +64,14 @@ int set_cpu_clk_info(void)
        return 0;
 }
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+       return readl(socfpga_get_sysmgr_addr() +
+                    SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+#endif
+
 #ifndef CONFIG_SPL_BUILD
 static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
                         char *const argv[])

diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c
index 6377f2ce3bf9cbe418624baca952a51e43eb4d8c..e035c09aaefe92a9396790c39432104d79747c38 100644 (file)
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -65,12 +65,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
        return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
 }
 
-u32 cm_get_qspi_controller_clk_hz(void)
-{
-       return readl(socfpga_get_sysmgr_addr() +
-                    SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
 void cm_print_clock_quick_summary(void)
 {
        printf("MPU       %10d kHz\n",

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index e060e5754e6351f98d0d2ee84e80bed108669544..4b4f0749dbf813010b22ceb1cfa6bbbf865823f3 100644 (file)
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -384,12 +384,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
        return clock;
 }
 
-unsigned int cm_get_qspi_controller_clk_hz(void)
-{
-       return readl(socfpga_get_sysmgr_addr() +
-                    SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
 unsigned int cm_get_spi_controller_clk_hz(void)
 {
        u32 clock = cm_get_l3_main_clk_hz();

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 1f734bcd65ef5df979e65602cc0ec5244b02b01d..9cf22375e3afe4ebc525903fb14aa61af16e205a 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
 void cm_wait_for_lock(u32 mask);
 int cm_wait_for_fsm(void);
 void cm_print_clock_quick_summary(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
 #endif
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index 11ddee5cb643f1e0468300fd48ed36d88b6f88f7..798d3741bd982341b4def2666476f5e700a4104c 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -70,8 +70,6 @@ int cm_basic_init(const void *blob);
 unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned long cm_get_mpu_clk_hz(void);
 
-unsigned int cm_get_qspi_controller_clk_hz(void);
-
 #endif /* __ASSEMBLY__ */
 
 #define LOCKED_MASK    (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 5c9abe619b90fd295491d1988864389b720e01e2..4cc1268b4c4d75bbb995d77f12e705e6628369ea 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -100,7 +100,6 @@ unsigned long cm_get_mpu_clk_hz(void);
 unsigned long cm_get_sdram_clk_hz(void);
 unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
 const unsigned int cm_get_osc_clk_hz(const int osc);
 const unsigned int cm_get_f2s_per_ref_clk_hz(void);

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index cb7923baef8c25d21cca49b8ff652d40eadd81d8..98c3bf1b03e1bf764bbf1303eed88b7f7199e70c 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void);
 unsigned long cm_get_sdram_clk_hz(void);
 unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
 
 struct cm_config {