mpc8569mds: fix consuming long time while relocating code.

The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle this, map the boot flash as
write-through cache via tlb. And set tlb to remap the flash after code
executing in ddr, to confirm flash erase operation properly done.

Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 01b7dcb70cb142b2aab16a4e6dcbfe97f2c18cb0..795e5654e8cd343182922c79769f86e8cf426f21 100644 (file)
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -27,6 +27,7 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
@@ -211,6 +212,31 @@ int board_early_init_f (void)
        return 0;
 }
 
+int board_early_init_r(void)
+{
+       const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+       const u8 flash_esel = 0;
+
+       /*
+        * Remap Boot flash to caching-inhibited
+        * so that flash can be erased properly.
+        */
+
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
+
+       /* invalidate existing TLB entry for flash */
+       disable_tlb(flash_esel);
+
+       set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,     /* tlb, epn, rpn */
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+               0, flash_esel,                          /* ts, esel */
+               BOOKE_PAGESZ_64M, 1);                   /* tsize, iprot */
+
+       return 0;
+}
+
 int checkboard (void)
 {
        printf ("Board: 8569 MDS\n");

diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index 73dcc3e66c5b4ebb484dfc09264b50cca4c7cd2b..f852fc35c35fd1a4992811e53ed6b6eaac032c0c 100644 (file)
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
        /* TLB 1 Initializations */
        /*
-        * TLBe 0:      64M     Non-cacheable, guarded
+        * TLBe 0:      64M     write-through, guarded
         * Out of reset this entry is only 4K.
-        * 0xfc000000   256K    NAND FLASH (CS3)
-        * 0xfe000000   32M     NOR FLASH (CS0)
+        * 0xfc000000   32MB    NAND FLASH (CS3)
+        * 0xfe000000   32MB    NOR FLASH (CS0)
         */
+#ifdef CONFIG_NAND_SPL
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
                      0, 0, BOOKE_PAGESZ_64M, 1),
-
+#endif
        /*
         * TLBe 1:      256KB   Non-cacheable, guarded
         * 0xf8000000   32K     BCSR

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 936f1af318269d58248475ff06e8fea712c94f06..95c0a9ffc4049b38203368d614df8845f6c613cb 100644 (file)
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -74,6 +74,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_ENABLE_36BIT_PHYS       1
 
 #define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R      1
 #define CONFIG_HWCONFIG
 
 #define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */