avr32: Rename pm_init() as clk_init() and make SoC-specific

pm_init() was always more about clock initialization than anything
else. Dealing with PLLs, clock gating and such is also inherently
SoC-specific, so move it into a SoC-specific directory.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>

diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile
index d2767121184acbe3b48127452e20695299065a40..740423563ed9d2411fde722946eb157714e83111 100644 (file)
--- a/cpu/at32ap/at32ap700x/Makefile
+++ b/cpu/at32ap/at32ap700x/Makefile
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB    := $(obj)lib$(SOC).a
 
-COBJS  := gpio.o
+COBJS  := gpio.o clk.o
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
 

diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c
new file mode 100644 (file)
index 0000000..b3aa034
--- /dev/null
+++ b/cpu/at32ap/at32ap700x/clk.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2005-2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/clk.h>
+#include <asm/arch/memory-map.h>
+
+#include "sm.h"
+
+void clk_init(void)
+{
+       uint32_t cksel;
+
+       /* in case of soft resets, disable watchdog */
+       sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
+       sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
+
+#ifdef CONFIG_PLL
+       /* Initialize the PLL */
+       sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
+                           | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
+                           | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
+                           | SM_BF(PLLOPT, CFG_PLL0_OPT)
+                           | SM_BF(PLLOSC, 0)
+                           | SM_BIT(PLLEN)));
+
+       /* Wait for lock */
+       while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
+#endif
+
+       /* Set up clocks for the CPU and all peripheral buses */
+       cksel = 0;
+       if (CFG_CLKDIV_CPU)
+               cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
+       if (CFG_CLKDIV_HSB)
+               cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
+       if (CFG_CLKDIV_PBA)
+               cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
+       if (CFG_CLKDIV_PBB)
+               cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
+       sm_writel(PM_CKSEL, cksel);
+
+#ifdef CONFIG_PLL
+       /* Use PLL0 as main clock */
+       sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
+#endif
+}

diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/at32ap700x/sm.h
similarity index 100%
rename from cpu/at32ap/sm.h
rename to cpu/at32ap/at32ap700x/sm.h

diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c
index a7a66cc1a0b028b2677f542a9521409c5005c238..0ba836180e4396f61891f76f7dda42ac64717edf 100644 (file)
--- a/cpu/at32ap/cpu.c
+++ b/cpu/at32ap/cpu.c
@@ -30,7 +30,6 @@
 #include <asm/arch/memory-map.h>
 
 #include "hsmc3.h"
-#include "sm.h"
 
 /* Sanity checks */
 #if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB)          \
@@ -44,51 +43,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void pm_init(void)
-{
-       uint32_t cksel;
-
-#ifdef CONFIG_PLL
-       /* Initialize the PLL */
-       sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
-                           | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
-                           | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
-                           | SM_BF(PLLOPT, CFG_PLL0_OPT)
-                           | SM_BF(PLLOSC, 0)
-                           | SM_BIT(PLLEN)));
-
-       /* Wait for lock */
-       while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
-#endif
-
-       /* Set up clocks for the CPU and all peripheral buses */
-       cksel = 0;
-       if (CFG_CLKDIV_CPU)
-               cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
-       if (CFG_CLKDIV_HSB)
-               cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
-       if (CFG_CLKDIV_PBA)
-               cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
-       if (CFG_CLKDIV_PBB)
-               cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
-       sm_writel(PM_CKSEL, cksel);
-
-       gd->cpu_hz = get_cpu_clk_rate();
-
-#ifdef CONFIG_PLL
-       /* Use PLL0 as main clock */
-       sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
-#endif
-}
-
 int cpu_init(void)
 {
        extern void _evba(void);
 
-       /* in case of soft resets, disable watchdog */
-       sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
-       sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
-
        gd->cpu_hz = CFG_OSC0_HZ;
 
        /* TODO: Move somewhere else, but needs to be run before we
@@ -98,8 +56,12 @@ int cpu_init(void)
        hsmc3_writel(PULSE0, 0x0b0a0906);
        hsmc3_writel(SETUP0, 0x00010002);
 
-       pm_init();
+       clk_init();
+
+       /* Update the CPU speed according to the PLL configuration */
+       gd->cpu_hz = get_cpu_clk_rate();
 
+       /* Set up the exception handler table and enable exceptions */
        sysreg_write(EVBA, (unsigned long)&_evba);
        asm volatile("csrf      %0" : : "i"(SYSREG_EM_OFFSET));
 

diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index 309fda50e21d7613e5ed68134994fe9338c94f62..4a1dd33b56b0c259b7bbebb91ef8e5a9ae02524c 100644 (file)
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -75,6 +75,8 @@ static inline unsigned long get_mci_clk_rate(void)
 }
 #endif
 
+extern void clk_init(void);
+
 /* Board code may need the SDRAM base clock as a compile-time constant */
 #define SDRAMC_BUS_HZ  (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)