]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
Define tsec flag values in config files
authorAndy Fleming <afleming@freescale.com>
Thu, 16 Aug 2007 01:03:25 +0000 (20:03 -0500)
committerWolfgang Denk <wd@denx.de>
Thu, 16 Aug 2007 10:12:49 +0000 (12:12 +0200)
The tsec_info structure and array has a "flags" field for each
ethernet controller.  This field is the only reason there are
settings.  Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.

Signed-off-by: Andy Fleming <afleming@freescale.com>
21 files changed:
drivers/tsec.c
include/configs/MPC8313ERDB.h
include/configs/MPC8349EMDS.h
include/configs/MPC8349ITX.h
include/configs/MPC8540ADS.h
include/configs/MPC8540EVAL.h
include/configs/MPC8541CDS.h
include/configs/MPC8544DS.h
include/configs/MPC8548CDS.h
include/configs/MPC8555CDS.h
include/configs/MPC8560ADS.h
include/configs/MPC8568MDS.h
include/configs/MPC8641HPCN.h
include/configs/PM854.h
include/configs/PM856.h
include/configs/TQM834x.h
include/configs/TQM85xx.h
include/configs/sbc8349.h
include/configs/sbc8641d.h
include/configs/stxgp3.h
include/configs/stxssa.h

index fd21ed4edc401a2e86504c1a9b3579e676ce26c7..1df8f7dc256d5a08f0344ea66f14aefcf4af4778 100644 (file)
@@ -65,38 +65,30 @@ struct tsec_info_struct {
  *   FEC_PHYIDX
  */
 static struct tsec_info_struct tsec_info[] = {
-#if defined(CONFIG_TSEC1)
-#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
-       {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
-#else
-       {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
-#endif
+#ifdef CONFIG_TSEC1
+       {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
 #else
        {0, 0, 0},
 #endif
-#if defined(CONFIG_TSEC2)
-#if defined(CONFIG_MPC8641HPCN)
-       {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
-#else
-       {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
-#endif
+#ifdef CONFIG_TSEC2
+       {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
 #else
        {0, 0, 0},
 #endif
 #ifdef CONFIG_MPC85XX_FEC
-       {FEC_PHY_ADDR, 0, FEC_PHYIDX},
+       {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
 #else
-#if defined(CONFIG_TSEC3)
-       {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
+#ifdef CONFIG_TSEC3
+       {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
 #else
        {0, 0, 0},
 #endif
-#if defined(CONFIG_TSEC4)
-       {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
+#ifdef CONFIG_TSEC4
+       {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
 #else
        {0, 0, 0},
-#endif
-#endif
+#endif /* CONFIG_TSEC4 */
+#endif /* CONFIG_MPC85XX_FEC */
 };
 
 #define MAXCONTROLLERS (4)
index 81db96f4661e79d4cae14a1c9b103f01006c46ab..f92dce541f859d8eeb03e5263afee59cbfa09d5b 100644 (file)
 #define CONFIG_TSEC2_NAME      "TSEC1"
 #define TSEC1_PHY_ADDR                 0x1c
 #define TSEC2_PHY_ADDR                 4
+#define TSEC1_FLAGS                    TSEC_GIGABIT
+#define TSEC2_FLAGS                    TSEC_GIGABIT
 #define TSEC1_PHYIDX                   0
 #define TSEC2_PHYIDX                   0
 
index 1567fcfae32cfca9a1248d38d38fe95ee139611f..10af5f0bc8a7e50114bd7c785b1a4fc583509edc 100644 (file)
 #define TSEC2_PHY_ADDR         1
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                "TSEC0"
index 44649d05090b9a2cfeb7b84c6cdc699c26625334..58ee13d3f37b0c7d1b6574b788fe59a02c6e7dd4 100644 (file)
@@ -382,6 +382,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_TSEC1_OFFSET       0x24000
 #define TSEC1_PHY_ADDR         0x1c    /* VSC8201 uses address 0x1c */
 #define TSEC1_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
 #endif
 
 #ifdef CONFIG_TSEC2
@@ -391,6 +392,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_UNKNOWN_TSEC    /* TSEC2 is proprietary */
 #define TSEC2_PHY_ADDR         4
 #define TSEC2_PHYIDX           0
+#define TSEC2_FLAGS            TSEC_GIGABIT
 #endif
 
 #define CONFIG_ETHPRIME                "Freescale TSEC"
index 5a7c879a53305ad8865da5b5a5be3d77c8de8ef9..b7749926717f38ba2c29da3a6173d00870bbdcb2 100644 (file)
 #define TSEC2_PHY_ADDR         1
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 
 #if CONFIG_HAS_FEC
 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 #define FEC_PHY_ADDR           3
 #define FEC_PHYIDX             0
+#define FEC_FLAGS              0
 #endif
 
 /* Options are: TSEC[0-1], FEC */
index 0ce25cf24e74f7ffec61e3ca2e1503d0dc6ad1ac..5c03ac8c95e99bff653f46bdbaea2f54cb15a5dd 100644 (file)
 #define TSEC1_PHYIDX            0
 #define TSEC2_PHYIDX            0
 #define FEC_PHYIDX              0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
+#define FEC_FLAGS              0
+
 /* Options are: TSEC[0-1], FEC */
 #define CONFIG_ETHPRIME                "TSEC0"
 
index 232f1716bcc34edf38df841b1474bc9ab6107958..33a153e3460621c92bec05e33c7cf6eb37d25bd2 100644 (file)
@@ -384,13 +384,12 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_TSEC1_NAME      "TSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "TSEC1"
-#undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR         0
 #define TSEC2_PHY_ADDR         1
-#define FEC_PHY_ADDR           3
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
-#define FEC_PHYIDX             0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                "TSEC0"
index 32934e15506540a19b506ff248a1bb05103fd468..78634473317e2df2063bafb81282f3456647c0dc 100644 (file)
@@ -364,15 +364,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_TSEC1_NAME      "eTSEC1"
 #define CONFIG_TSEC3   1
 #define CONFIG_TSEC3_NAME      "eTSEC3"
-#undef CONFIG_MPC85XX_FEC
-
-#define CONFIG_TSEC_TBI                1       /* enable internal TBI phy */
-#define CONFIG_SGMII_RISER
-#define TSEC1_SGMII_PHY_ADDR_OFFSET    0x1c    /* sgmii phy base */
 
 #define TSEC1_PHY_ADDR         0
 #define TSEC3_PHY_ADDR         1
 
+#define TSEC1_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+
 #define TSEC1_PHYIDX           0
 #define TSEC3_PHYIDX           0
 
index cda9fd5c1c78664efe47151fe8e891896e885eab..7345a3e10f029d831bed755601adf209c7162f33 100644 (file)
@@ -447,6 +447,10 @@ extern unsigned long get_clock_freq(void);
 #define TSEC2_PHYIDX           0
 #define TSEC3_PHYIDX           0
 #define TSEC4_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
+#define TSEC3_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
 
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME                "eTSEC0"
index e8fe99aaf13333457dc285da3cd92d5b33bf4caf..48a2663b5c65f289b4e992cbe6229e647e17d230 100644 (file)
@@ -384,13 +384,12 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_TSEC1_NAME      "TSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "TSEC1"
-#undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR         0
 #define TSEC2_PHY_ADDR         1
-#define FEC_PHY_ADDR           3
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
-#define FEC_PHYIDX             0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                "TSEC0"
index c10e551e408d2cd01a1c3918d6fd60d226af7bea..da41dadcd27af124edaadaecad7b1c12f6efb484 100644 (file)
 #define CONFIG_TSEC1_NAME      "TSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "TSEC1"
-#undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR         0
 #define TSEC2_PHY_ADDR         1
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                "TSEC0"
index dc9cb1ff54550fc98fd830d433da2f4fa3098f3f..6b824ed9ddb0a9b2e12dc06e09acba21ef04fbec 100644 (file)
@@ -399,9 +399,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_TSEC1_NAME      "eTSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "eTSEC1"
-#undef  CONFIG_TSEC3
-#undef  CONFIG_TSEC4
-#undef  CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR         2
 #define TSEC2_PHY_ADDR         3
@@ -409,6 +406,9 @@ extern unsigned long get_clock_freq(void);
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
 
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
+
 /* Options are: eTSEC[0-3] */
 #define CONFIG_ETHPRIME                "eTSEC0"
 
index 64dcbd010934d062f17b2677fb020e6ecfaa41f8..e912331f31c309a06c13ec66d40efabcb1455bcb 100644 (file)
@@ -417,6 +417,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define TSEC2_PHYIDX           0
 #define TSEC3_PHYIDX           0
 #define TSEC4_PHYIDX           0
+#define TSEC1_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
 
 #define CONFIG_ETHPRIME                "eTSEC1"
 
index dbf94228ae658fb09cbe08f83f5014a0579fe209..93090b981c3e80425856f864b32796e75180e050 100644 (file)
 #define TSEC2_PHY_ADDR         1
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 #define CONFIG_MPC85XX_FEC     1
 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 #define FEC_PHY_ADDR           3
 #define FEC_PHYIDX             0
+#define FEC_FLAGS              0
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                "TSEC0"
index 6bdfa5d8f1ff175807e1c64c7697fd582e72726f..6105747c70e4c3d9f4be9a1c51c53c33e4e93595 100644 (file)
 #define CONFIG_TSEC1_NAME      "TSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "TSEC1"
-#undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR         0
 #define TSEC2_PHY_ADDR         1
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 #endif  /* CONFIG_TSEC_ENET */
 
index 661712b227b9e2ff7144b43cbd5818b18d20ea34..91c1694f2caca6b29a574f731fcb71ca28372281 100644 (file)
@@ -253,6 +253,8 @@ extern int tqm834x_num_flash_banks;
 #define TSEC2_PHY_ADDR                 1
 #define TSEC1_PHYIDX                   0
 #define TSEC2_PHYIDX                   0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                        "TSEC0"
index d5ce3ba7169932d9c64df0c3a22068a4f473f72c..cb9bf5492950eb89e186b95704cc9d3534af0177 100644 (file)
 #define TSEC2_PHY_ADDR         1
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 #define FEC_PHY_ADDR           3
 #define FEC_PHYIDX             0
+#define FEC_FLAGS              0
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
 
index 1831bef0de11ad91e490437b791bcdbc04be52dd..aa515ea6148eac6d24f18f251c2111fba2a2227d 100644 (file)
 #define TSEC2_PHY_ADDR         0x1a
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME                "TSEC0"
index 277b611409d877e790301730c348ac8cf5330a14..760b754e6c5f91dcec9a7069b98f19a96a5edcca 100644 (file)
 #define TSEC2_PHYIDX           0
 #define TSEC3_PHYIDX           0
 #define TSEC4_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
+#define TSEC3_FLAGS            TSEC_GIGABIT
+#define TSEC4_FLAGS            TSEC_GIGABIT
 
 #define CFG_TBIPA_VALUE        0x1e    /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
 
index 1f41cf7699e0ac4dac768d677790251c9a518754..43b185bee6f1feae744152635cc158813588e852 100644 (file)
 #define CONFIG_TSEC1_NAME      "TSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "TSEC1"
-#undef CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR         2
 #define TSEC2_PHY_ADDR         4
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 #define CONFIG_ETHPRIME                "TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)     /* CPM FCC Ethernet */
index 55e2c8da20dcffc1c5e2aa2bc64c707615675f54..3dae27ac11b54a635e094487c135625af5443d9f 100644 (file)
 #define CONFIG_TSEC1_NAME      "TSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "TSEC1"
-#define CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR         2
 #define TSEC2_PHY_ADDR         4
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
 #define CONFIG_ETHPRIME                "TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)     /* CPM FCC Ethernet */