armv8: lx2162a: Add Soc changes to support LX2162A

LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.

LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 3655990772c012bc456aee5cbcb8a52117845c12..f2474413ccab088d98ba4be0e70be5f255ae7688 100644 (file)
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -115,7 +115,7 @@ config PSCI_RESET
                   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
                   !TARGET_LS1046AFRWY && \
                   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
-                  !TARGET_LX2160AQDS && \
+                  !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
                   !ARCH_UNIPHIER && !TARGET_S32V234EVB
        help
          Most armv8 systems have PSCI support enabled in EL3, either through

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index be51b7d8566fe044ed11e0d6a74f0f286b72ecb2..4d465872140b11bf942d52706c7fd23bfd1eeffe 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -208,6 +208,35 @@ config ARCH_LS2080A
        imply DISTRO_DEFAULTS
        imply PANIC_HANG
 
+config ARCH_LX2162A
+       bool
+       select ARMV8_SET_SMPEN
+       select FSL_LSCH3
+       select NXP_LSCH3_2
+       select SYS_HAS_SERDES
+       select SYS_FSL_SRDS_1
+       select SYS_FSL_SRDS_2
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_LE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_EC1
+       select SYS_FSL_EC2
+       select SYS_FSL_ERRATUM_A050106
+       select SYS_FSL_HAS_RGMII
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_HAS_CCN508
+       select SYS_FSL_HAS_DDR4
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
+       select ARCH_EARLY_INIT_R
+       select BOARD_EARLY_INIT_F
+       select SYS_I2C_MXC
+       select RESV_RAM if GIC_V3_ITS
+       imply DISTRO_DEFAULTS
+       imply PANIC_HANG
+       imply SCSI
+       imply SCSI_AHCI
+
 config ARCH_LX2160A
        bool
        select ARMV8_SET_SMPEN
@@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106
        help
          USB3.0 Receiver needs to enable fixed equalization
          for each of PHY instances in an SOC. This is similar
-         to erratum A-009007, but this one is for LX2160A,
+         to erratum A-009007, but this one is for LX2160A and LX2162A,
          and the register value is different.
 
 config SYS_FSL_ERRATUM_A010315
@@ -362,6 +391,7 @@ config MAX_CPUS
        default 16 if ARCH_LS2080A
        default 8 if ARCH_LS1088A
        default 16 if ARCH_LX2160A
+       default 16 if ARCH_LX2162A
        default 1
        help
          Set this number to the maximum number of possible CPUs in the SoC.
@@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV
        int "DUART clock divider"
        default 1 if ARCH_LS1043A
        default 4 if ARCH_LX2160A
+       default 4 if ARCH_LX2162A
        default 2
        help
          This is the divider that is used to derive DUART clock from Platform
@@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV
        default 4 if ARCH_LS1012A
        default 4 if ARCH_LS1028A
        default 8 if ARCH_LX2160A
+       default 8 if ARCH_LX2162A
        default 8 if ARCH_LS1088A
        default 2
        help
@@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV
        default 4 if ARCH_LS1012A
        default 4 if ARCH_LS1028A
        default 8 if ARCH_LX2160A
+       default 8 if ARCH_LX2162A
        default 8 if ARCH_LS1088A
        default 2
        help
@@ -560,14 +593,14 @@ config SYS_FSL_EC1
        bool
        help
          Ethernet controller 1, this is connected to
-         MAC17 for LX2160A or to MAC3 for other SoCs
+         MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
          Provides DPAA2 capabilities
 
 config SYS_FSL_EC2
        bool
        help
          Ethernet controller 2, this is connected to
-         MAC18 for LX2160A or to MAC4 for other SoCs
+         MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
          Provides DPAA2 capabilities
 
 config SYS_FSL_ERRATUM_A008336

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 9ecb372b4e6adacdb1eddaa0bcf233a8e96f6717..598c36ee660a834f0507872071e12eb9b77792aa 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -27,6 +27,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
 obj-y += icid.o lx2160_ids.o
 endif
 
+ifneq ($(CONFIG_ARCH_LX2162A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
+obj-y += icid.o lx2160_ids.o
+endif
+
 ifneq ($(CONFIG_ARCH_LS2080A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
 obj-y += icid.o ls2088_ids.o

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 596b88d3e29c2ba91c2429ec4ccc92530463545b..1a5d26b5372e918ce27084fee5f44c118c944106 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
        CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
        CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
+       CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
+       CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
+       CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
 };
 
 #define EARLY_PGTABLE_SIZE 0x5000
@@ -403,7 +406,7 @@ void cpu_name(char *name)
        for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
                if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
                        strcpy(name, cpu_type_list[i].name);
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
                        if (IS_C_PROCESSOR(svr))
                                strcat(name, "C");
 #endif
@@ -1229,7 +1232,7 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 
 void __efi_runtime reset_cpu(ulong addr)
 {
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
        /* clear the RST_REQ_MSK and SW_RST_REQ */
        out_le32(rstcr, 0x0);
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index ad55573c85e050f1e3547df3fe484416ac054431..f33d05d0539fbff50631e9dbf9fb272beff62146 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -9,6 +9,7 @@ SoC overview
        7. LS2081A
        8. LX2160A
        9. LS1028A
+       10. LX2162A
 
 LS1043A
 ---------
@@ -379,3 +380,58 @@ The LS1028A SoC includes the following function and features:
   - Layerscape Trust Architecture
   - Service Processor (SP) provides pre-boot initialization and secure-boot
     capabilities
+
+LX2162A
+--------
+The QorIQ LX2162A processor is built on the Layerscape architecture
+combining sixteen ARM A72 processor cores with advanced, high-performance
+datapath acceleration and network, peripheral interfaces required for
+networking, wireless infrastructure, storage, and general-purpose embedded
+applications.
+
+LX2162A is compliant with the Layerscape Chassis Generation 3.2.
+
+The LX2162A SoC includes the following function and features:
+  Sixteen 32-bit / 64-bit ARM v8 A72 CPUs
+  Cache Coherent Interconnect Fabric (CCN508)
+  One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC.
+  Data path acceleration architecture (DPAA2)
+  12 Serdes lanes at up to 25 GHz
+  Ethernet interfaces
+  Support for 10G-SXGMII (aka USXGMII).
+  Support for SGMII (and 1000Base-KX)
+  Support for XFI (and 10GBase-KR)
+  Support for CAUI2 (50G) and 25G-AUI(25G).
+  Support for XLAUI (and 40GBase-KR4) for 40G.
+  Support for two RGMII parallel interfaces.
+  Energy efficient Ethernet support (802.3az)
+  IEEE 1588 support.
+  High-speed peripheral interfaces
+       One PCIe Gen 3.0 8-lane controllers supporting SR-IOV,
+       Two PCIe Gen 3.0 4-lane controllers.
+       Four serial ATA (SATA 3.0) controllers.
+       One USB 3.0 controllers with integrated PHY
+       Two Enhanced secure digital host controllers
+       Two Controller Area Network (CAN) modules
+       Flexible Serial peripheral interface (FlexSPI) controller.
+       Three Serial peripheral interface (SPI) controllers.
+       Eight I2C Controllers.
+       Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports.
+       General Purpose IO (GPIO)
+  Support for hardware virtualization and partitioning (ARM MMU-500)
+  Support for GIC (ARM GIC-500)
+  QorIQ platform Trust Architecture 3.0
+  One Secure WatchDog timer and one Non-Secure Watchdog timer.
+  ARM Generic Timer
+  Two Flextimers
+  Debug supporting run control, data acquisition, high-speed trace,
+  performance/event monitoring
+  Thermal Monitor Unit (TMU) with +/- 2C accuracy
+  Support for Voltage ID (VID) for yield improvement
+
+LX2162A SoC has 2 more similar SoC personalities
+1)LX2122A, few difference w.r.t. LX2162A:
+       a) Twelve 64-bit ARM v8 Cortex-A72 CPUs
+
+2)LX2082A, few difference w.r.t. LX2162A:
+       a) Eight 64-bit ARM v8 Cortex-A72 CPUs

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index aa6fd6b28ce1627c7169f1381e31ed22c5d314cc..fad7a935662d61b9f6f983e6972bf9df6bd52b40 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2018, 2020 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  */
 
@@ -26,7 +26,7 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
 
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 int xfi_dpmac[XFI14 + 1];
 int sgmii_dpmac[SGMII18 + 1];
 int a25gaui_dpmac[_25GE10 + 1];
@@ -159,7 +159,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
                else {
                        serdes_prtcl_map[lane_prtcl] = 1;
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
                        if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
                                wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
                                                 (int)lane_prtcl);
@@ -552,7 +552,7 @@ void fsl_serdes_init(void)
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
        int i , j;
 
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
        for (i = XFI1, j = 1; i <= XFI14; i++, j++)
                xfi_dpmac[i] = j;
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 7f8178f72ebdef7a8c8c6888e38c3f3fcbe65fc7..bf153c720e13d7675e726dc7e638b26cb7f51d47 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015, Freescale Semiconductor, Inc.
- * Copyright 2019 NXP Semiconductors
+ * Copyright 2019-2020 NXP
  *
  * Derived from arch/power/cpu/mpc85xx/speed.c
  */
@@ -180,7 +180,7 @@ int get_clocks(void)
 #ifdef CONFIG_FSL_ESDHC
 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
        clock = sys_info.freq_cga_m2;
-#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
        clock = sys_info.freq_systembus;
 #endif
        gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
index a04a370268b1f19abfb164cf46f63a0b2676412b..5941d90e036fdfb82cda7e5ee94b1972af68dc18 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
  */
 
 #include <common.h>
@@ -11,6 +11,22 @@ struct serdes_config {
        u8 lanes[SRDS_MAX_LANES];
 };
 
+#if defined(CONFIG_ARCH_LX2162A)
+static struct serdes_config serdes1_cfg_tbl[] = {
+       /* SerDes 1 */
+       {0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+       {0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
+       {0x03, {XFI6, XFI5, XFI4, XFI3 } },
+       {0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
+       {0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
+       {0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
+       {0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
+       {0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
+       {0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
+       {0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } },
+       {}
+};
+#else
 static struct serdes_config serdes1_cfg_tbl[] = {
        /* SerDes 1 */
        {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
@@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
        {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
        {}
 };
+#endif
 
 static struct serdes_config serdes2_cfg_tbl[] = {
        /* SerDes 2 */

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 96b2775f3f985bbb11ec3f1fe8b5bd13a19a7336..ad209bde334c4c9692ea48b30ee5a4ab48cefab7 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 #include <common.h>
@@ -186,7 +186,8 @@ static void erratum_a008997(void)
        out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
 
 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
-       defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
+       defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
+       defined(CONFIG_ARCH_LX2162A)
 
 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)     \
        out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
@@ -222,7 +223,7 @@ static void erratum_a009007(void)
 #if defined(CONFIG_FSL_LSCH3)
 static void erratum_a050106(void)
 {
-#if defined(CONFIG_ARCH_LX2160A)
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
        void __iomem *dcsr = (void __iomem *)DCSR_BASE;
 
        PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
@@ -392,7 +393,8 @@ void fsl_lsch3_early_init_f(void)
 #endif
 
 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
-       defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+       defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
+       defined(CONFIG_ARCH_LX2162A)
        set_icids();
 #endif
 }

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index e13f4d83e69c2c67e1eb04d50755362d6e90734c..a9bd8b24fdc7203af21bab1adb5e7613353e4784 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2018, 2020 NXP
  * Copyright 2015, Freescale Semiconductor
  */
 
@@ -179,8 +179,8 @@
 #define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE      0x00020000 /* Real size 128K */
 
-/* LX2160A Soc Support */
-#elif defined(CONFIG_ARCH_LX2160A)
+/* LX2160A/LX2162A Soc Support */
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define TZPC_BASE                              0x02200000
 #define TZPCDECPROT_0_SET_BASE                 (TZPC_BASE + 0x804)
 #if !defined(CONFIG_DM_I2C)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 7759acdb8f6bafb274f7ba749cc3ffa9be8a1119..4335aa0ec28f382bdc52fdad12aae8ae8f88f656 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2020 NXP
  * Copyright 2014-2015, Freescale Semiconductor
  */
 
@@ -53,7 +53,7 @@
 #define CONFIG_SYS_FSL_WRIOP1_SIZE     0x100000000
 #define CONFIG_SYS_FSL_AIOP1_BASE      0x4b00000000
 #define CONFIG_SYS_FSL_AIOP1_SIZE      0x100000000
-#ifndef CONFIG_ARCH_LX2160A
+#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
 #define CONFIG_SYS_FSL_PEBUF_BASE      0x4c00000000
 #else
 #define CONFIG_SYS_FSL_PEBUF_BASE      0x1c00000000

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 24a64b75752679f7e3461d5b10876c8e8e8b91bb..b61666ed4b72994d96b7725d9709cc3d807f9df1 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -2,7 +2,7 @@
 /*
  * LayerScape Internal Memory Map
  *
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014 Freescale Semiconductor, Inc.
  */
 
@@ -15,7 +15,7 @@
 #define CONFIG_SYS_FSL_DDR3_ADDR               0x08210000
 #define CONFIG_SYS_FSL_GUTS_ADDR               (CONFIG_SYS_IMMR + 0x00E00000)
 #define CONFIG_SYS_FSL_PMU_ADDR                        (CONFIG_SYS_IMMR + 0x00E30000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define CONFIG_SYS_FSL_RST_ADDR                        (CONFIG_SYS_IMMR + 0x00e88180)
 #else
 #define CONFIG_SYS_FSL_RST_ADDR                        (CONFIG_SYS_IMMR + 0x00E60000)
@@ -198,12 +198,12 @@
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_PCIE4_ADDR                  (CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define SYS_PCIE5_ADDR                         (CONFIG_SYS_IMMR + 0x2800000)
 #define SYS_PCIE6_ADDR                         (CONFIG_SYS_IMMR + 0x2900000)
 #endif
 
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x9000000000ULL
@@ -267,7 +267,7 @@
        defined(CONFIG_ARCH_LS1028A)
 #define USB_PHY_RX_EQ_VAL_3            0x0380
 #define USB_PHY_RX_EQ_VAL_4            0x0b80
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define USB_PHY_RX_EQ_VAL_3            0x0080
 #define USB_PHY_RX_EQ_VAL_4            0x0880
 #endif
@@ -391,7 +391,7 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR       29
 #define FSL_CHASSIS3_SRDS2_REGSR       29
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define FSL_CHASSIS3_EC1_REGSR  27
 #define FSL_CHASSIS3_EC2_REGSR  27
 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK      0x00000003

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 020548ac6ce635b122cbc0f9865292132286fd60..b24f38cac908df95bd7ad1f3c1278c8b85c7b844 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2015 Freescale Semiconductor
  */
 
@@ -106,13 +106,16 @@ enum boot_src get_boot_src(void);
 #define SVR_LX2160A            0x873600
 #define SVR_LX2120A            0x873620
 #define SVR_LX2080A            0x873602
+#define SVR_LX2162A            0x873608
+#define SVR_LX2122A            0x873628
+#define SVR_LX2082A            0x87360A
 
 #define SVR_MAJ(svr)           (((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)           (((svr) >> 0) & 0xf)
 #define SVR_REV(svr)           (((svr) >> 0) & 0xff)
 #define SVR_SOC_VER(svr)       (((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)    (!((svr >> 8) & 0x1))
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define IS_C_PROCESSOR(svr)    (!((svr >> 12) & 0x1))
 #endif
 #ifdef CONFIG_ARCH_LS1028A

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 4c54e3d3d5e7d3eace88924a8f8886cb3831dbca..36f36699a7cc7ddc045d48dc80ea227c569e74e2 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2015-2019 NXP
+ * Copyright 2015-2020 NXP
  * Copyright 2014 Freescale Semiconductor, Inc.
  *
  */
@@ -74,11 +74,13 @@
 #define FSL_SDMMC_STREAM_ID            3
 #define FSL_SATA1_STREAM_ID            4
 
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
+       defined(CONFIG_ARCH_LX2162A)
 #define FSL_SATA2_STREAM_ID            5
 #endif
 
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
+       defined(CONFIG_ARCH_LX2162A)
 #define FSL_DMA_STREAM_ID              6
 #elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
 #define FSL_DMA_STREAM_ID              5
@@ -91,7 +93,7 @@
 #define FSL_PEX_STREAM_ID_END          22
 #elif defined(CONFIG_ARCH_LS1088A)
 #define FSL_PEX_STREAM_ID_END          18
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define FSL_PEX_STREAM_ID_END          (0x100)
 #endif
 

diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 9c51f5026083a4adcefbec101fb467b1b95abd31..77a3be68ef78abfbdf8d97967ff7c29a0a78b075 100644 (file)
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -487,7 +488,7 @@ int adjust_vdd(ulong vdd_override)
        int ret, i2caddress;
        unsigned long vdd_string_override;
        char *vdd_string;
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
        static const u16 vdd[32] = {
                8250,
                7875,

diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index f75d97b15c4daf5fd9899a920c3c806b1fcb21f7..5f62489a90f6ab71d121252e431589911a02cebd 100644 (file)
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -47,6 +47,7 @@ config SYS_NUM_DDR_CTLRS
                        ARCH_P5020      || \
                        ARCH_P5040      || \
                        ARCH_LX2160A    || \
+                       ARCH_LX2162A    || \
                        ARCH_T4160
        default 1
 

diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig
index 2cf651d3b3ee982b44ef79f9cec283ba032b4d47..ae4c35799bf765eb0b83e79bc8b131b8597bccde 100644 (file)
--- a/drivers/net/fsl-mc/Kconfig
+++ b/drivers/net/fsl-mc/Kconfig
@@ -4,7 +4,7 @@
 
 menuconfig FSL_MC_ENET
        bool "NXP Management Complex"
-       depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
+       depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A
        default y
        select RESV_RAM
        help
@@ -17,7 +17,7 @@ if FSL_MC_ENET
 config SYS_MC_RSV_MEM_ALIGN
        hex "Management Complex reserved memory alignment"
        depends on RESV_RAM
-       default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
+       default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A
        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.

diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 1d85b2cfa8a3d7de2afa01dc7cff40526671c832..52ab828f0b83564e47b26b0c3a2e86ba66e3b3a6 100644 (file)
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -7,3 +7,4 @@ obj-y += ldpaa_eth.o
 obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
 obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
 obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o
+obj-$(CONFIG_ARCH_LX2162A) += lx2160a.o

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index af927849508377259372d8307e142414241fbaaa..65498bce1d9a25ba28e934e3798cbaf043e5a1b5 100644 (file)
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -219,7 +219,7 @@ config FSL_PCIE_COMPAT
        default "fsl,ls1046a-pcie" if ARCH_LS1046A
        default "fsl,ls2080a-pcie" if ARCH_LS2080A
        default "fsl,ls1088a-pcie" if ARCH_LS1088A
-       default "fsl,lx2160a-pcie" if ARCH_LX2160A
+       default "fsl,lx2160a-pcie" if ARCH_LX2160A || ARCH_LX2162A
        default "fsl,ls1021a-pcie" if ARCH_LS1021A
        help
          This compatible is used to find pci controller node in Kernel DT
@@ -228,7 +228,7 @@ config FSL_PCIE_COMPAT
 config FSL_PCIE_EP_COMPAT
        string "PCIe EP compatible of Kernel DT"
        depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4
-       default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
+       default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A || ARCH_LX2162A
        default "fsl,ls-pcie-ep"
        help
          This compatible is used to find pci controller ep node in Kernel DT

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index 26c04a9fc27cd084d4824ead4841e97aa1f5d0a4..d7d4a44b228967ae1942b98d25cd0b270d887261 100644 (file)
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -273,7 +273,9 @@ static int ls_pcie_ep_probe(struct udevice *dev)
 
        svr = SVR_SOC_VER(get_svr());
 
-       if (svr == SVR_LX2160A)
+       if (svr == SVR_LX2160A || svr == SVR_LX2162A ||
+           svr == SVR_LX2120A || svr == SVR_LX2080A ||
+           svr == SVR_LX2122A || svr == SVR_LX2082A)
                pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
        else
                pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET;

diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c
index 0a42997696bfc35b7277d09dd362b076c09346c8..77d1573ea5a22adf81138b119b7eeb829b79d40f 100644 (file)
--- a/drivers/pci/pcie_layerscape_fixup_common.c
+++ b/drivers/pci/pcie_layerscape_fixup_common.c
@@ -121,13 +121,16 @@ int pcie_board_fix_fdt(void *fdt)
 
        svr = SVR_SOC_VER(get_svr());
 
-       if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 2, 0))
+       if ((svr == SVR_LX2160A || svr == SVR_LX2162A ||
+            svr == SVR_LX2120A || svr == SVR_LX2080A ||
+            svr == SVR_LX2122A || svr == SVR_LX2082A) &&
+            IS_SVR_REV(get_svr(), 2, 0))
                return lx2_board_fix_fdt(fdt);
 
        return 0;
 }
 
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 /* returns the next available streamid for pcie, -errno if failed */
 int pcie_next_streamid(int currentid, int idx)
 {