MPC85xx BA bits not set for 3-bit bank address DIMM

The current implementation does not set the number of bank address bits
(BA) in the processor. The default assumes 2 logical bank bits. This
works fine for a DIMM that uses devices with 4 internal banks (SPD
byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
devices with 8 internal banks (SPD byte17 = 0x8).

Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>

diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index d98455401a0822cfc27524f6d824443630c712d3..679f3608f72e40c4766f022bf1822ae27303f7be 100644 (file)
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -176,7 +176,7 @@ spd_sdram(void)
        spd_eeprom_t spd;
        unsigned int n_ranks;
        unsigned int rank_density;
-       unsigned int odt_rd_cfg, odt_wr_cfg;
+       unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
        unsigned int odt_cfg, mode_odt_enable;
        unsigned int refresh_clk;
 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
@@ -341,9 +341,14 @@ spd_sdram(void)
 #endif
        }
 
+       ba_bits = 0;
+       if (spd.nbanks == 0x8)
+               ba_bits = 1;
+
        ddr->cs0_config = ( 1 << 31
                            | (odt_rd_cfg << 20)
                            | (odt_wr_cfg << 16)
+                           | (ba_bits << 14)
                            | (spd.nrow_addr - 12) << 8
                            | (spd.ncol_addr - 8) );
        debug("\n");