OMAP4+: Force DDR in self-refresh after warm reset

Errata ID:i727

Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.

Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.

This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index edc63fa9cb5aa72f7a77c84a0bf426973d3b0977..64427e61dad18b4c02aa139704e79bcb73c2504c 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -32,6 +32,27 @@
 #include <asm/omap_common.h>
 #include <asm/utils.h>
 
+void set_lpmode_selfrefresh(u32 base)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+       u32 reg;
+
+       reg = readl(&emif->emif_pwr_mgmt_ctrl);
+       reg &= ~EMIF_REG_LP_MODE_MASK;
+       reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
+       reg &= ~EMIF_REG_SR_TIM_MASK;
+       writel(reg, &emif->emif_pwr_mgmt_ctrl);
+
+       /* dummy read for the new SR_TIM to be loaded */
+       readl(&emif->emif_pwr_mgmt_ctrl);
+}
+
+void force_emif_self_refresh()
+{
+       set_lpmode_selfrefresh(EMIF1_BASE);
+       set_lpmode_selfrefresh(EMIF2_BASE);
+}
+
 inline u32 emif_num(u32 base)
 {
        if (base == EMIF1_BASE)

diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 660032330ef0563ea9af5440f2ff14a8afef1385..459ebb55e572ab7bf78eb16f59a45b259ef28154 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -111,6 +111,10 @@ static void init_boot_params(void)
 void s_init(void)
 {
        init_omap_revision();
+#ifdef CONFIG_SPL_BUILD
+       if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+               force_emif_self_refresh();
+#endif
        watchdog_init();
        set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4f0a29da7fa59c58002b1be2881faac9819831dd..d633573c258b3b0e781dc93b681266d04d617e25 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -58,6 +58,7 @@ void do_io_settings(void);
 void omap_vc_init(u16 speed_khz);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
+void force_emif_self_refresh(void);
 /*
  * This is used to verify if the configuration header
  * was executed by Romcode prior to control of transfer

diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index b3bbdb7cd8db34f88b9f958e7db0afea76c7705c..74feb90277c993b0cda2bafe230db2a3bccf14a5 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -58,6 +58,7 @@ void do_io_settings(void);
 void omap_vc_init(u16 speed_khz);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
+void force_emif_self_refresh(void);
 
 /*
  * This is used to verify if the configuration header