ADS5121e: DDR2 init/timing update.

Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>

diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 1582c220679dd8797c1407858eff94b53ecdc0a8..462f41d3d2af2a0ebb63f6993770969c2fa48410 100644 (file)
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -126,24 +126,24 @@ long int fixed_sdram (void)
        im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
        im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
        im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
-       im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
-       im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
-       im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
-       im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
        im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
+       im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
        im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
+       im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
        im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
+       im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
        im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
+       im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
        im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
        im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
-       im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
-       im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
-       im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
-       im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
        im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
+       im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
        im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
+       im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
        im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
+       im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
        im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
+       im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
        im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
 
        /* Initialize MDDRC */
@@ -156,19 +156,27 @@ long int fixed_sdram (void)
        for (i = 0; i < 10; i++)
                im->mddrc.ddr_command = CFG_MICRON_NOP;
 
+       im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
+       im->mddrc.ddr_command = CFG_MICRON_NOP;
+       im->mddrc.ddr_command = CFG_MICRON_RFSH;
+       im->mddrc.ddr_command = CFG_MICRON_NOP;
+       im->mddrc.ddr_command = CFG_MICRON_RFSH;
+       im->mddrc.ddr_command = CFG_MICRON_NOP;
+       im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
+       im->mddrc.ddr_command = CFG_MICRON_NOP;
+       im->mddrc.ddr_command = CFG_MICRON_EM2;
+       im->mddrc.ddr_command = CFG_MICRON_NOP;
        im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
        im->mddrc.ddr_command = CFG_MICRON_EM2;
        im->mddrc.ddr_command = CFG_MICRON_EM3;
        im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
-       im->mddrc.ddr_command = CFG_MICRON_RST_DLL;
+       im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
        im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
        im->mddrc.ddr_command = CFG_MICRON_RFSH;
        im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
        im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
-       im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT;
-
-       for (i = 0; i < 10; i++)
-               im->mddrc.ddr_command = CFG_MICRON_NOP;
+       im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
+       im->mddrc.ddr_command = CFG_MICRON_NOP;
 
        /* Start MDDRC */
        im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;

diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 973f348dd5cf50f5c9cc16325628c1d1b3812090..8d90ea18e39782ea639ef942a6778706644e9025 100644 (file)
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -109,25 +109,22 @@
  *     [04:00] DRAM tRPA
  */
 
-#define CFG_MDDRC_SYS_CFG      0xF8604200
-#define CFG_MDDRC_SYS_CFG_RUN  0xE8604200
-#define CFG_MDDRC_SYS_CFG_EN   0x30000000
-#define CFG_MDDRC_TIME_CFG0    0x0000281E
-#define CFG_MDDRC_TIME_CFG0_RUN        0x01F4281E
+#define CFG_MDDRC_SYS_CFG      0xF8604A00
+#define CFG_MDDRC_SYS_CFG_RUN  0xE8604A00
+#define CFG_MDDRC_SYS_CFG_EN   0xF0000000
+#define CFG_MDDRC_TIME_CFG0    0x00003D2E
+#define CFG_MDDRC_TIME_CFG0_RUN        0x06183D2E
 #define CFG_MDDRC_TIME_CFG1    0x54EC1168
 #define CFG_MDDRC_TIME_CFG2    0x35210864
 
 #define CFG_MICRON_NOP         0x01380000
 #define CFG_MICRON_PCHG_ALL    0x01100400
-#define CFG_MICRON_MR          0x01000022
 #define CFG_MICRON_EM2         0x01020000
 #define CFG_MICRON_EM3         0x01030000
 #define CFG_MICRON_EN_DLL      0x01010000
-#define CFG_MICRON_RST_DLL     0x01000932
 #define CFG_MICRON_RFSH                0x01080000
-#define CFG_MICRON_INIT_DEV_OP 0x01000832
+#define CFG_MICRON_INIT_DEV_OP 0x01000432
 #define CFG_MICRON_OCD_DEFAULT 0x01010780
-#define CFG_MICRON_OCD_EXIT    0x01010400
 
 /* DDR Priority Manager Configuration */
 #define CFG_MDDRCGRP_PM_CFG1   0x000777AA