mx28: Remove SET, CLR, TOG ops from PLLxCTRL1 registers

These registers don't have _SET, _CLR and _TOG at the respective offsets
available, these registers has to be toggled via R-M-W if needed. Thus do
not export these offsets anymore.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
index b662fbe440049cbb2d9a7743d099c29f867d57b1..23e9adc25a28ee1cf8251b4b00ef70fe6bb67d46 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -31,9 +31,11 @@
 #ifndef        __ASSEMBLY__
 struct mxs_clkctrl_regs {
        mxs_reg_32(hw_clkctrl_pll0ctrl0)        /* 0x00 */
-       mxs_reg_32(hw_clkctrl_pll0ctrl1)        /* 0x10 */
+       uint32_t        hw_clkctrl_pll0ctrl1;   /* 0x10 */
+       uint32_t        reserved_pll0ctrl1[3];  /* 0x14-0x1c */
        mxs_reg_32(hw_clkctrl_pll1ctrl0)        /* 0x20 */
-       mxs_reg_32(hw_clkctrl_pll1ctrl1)        /* 0x30 */
+       uint32_t        hw_clkctrl_pll1ctrl1;   /* 0x30 */
+       uint32_t        reserved_pll1ctrl1[3];  /* 0x34-0x3c */
        mxs_reg_32(hw_clkctrl_pll2ctrl0)        /* 0x40 */
        mxs_reg_32(hw_clkctrl_cpu)              /* 0x50 */
        mxs_reg_32(hw_clkctrl_hbus)             /* 0x60 */