]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arch: m68k: Use existing CONFIG_MCFTMR instead of CFG_MCFTMR
authorMarek Vasut <marek.vasut+renesas@mailbox.org>
Thu, 23 Mar 2023 00:20:39 +0000 (01:20 +0100)
committerAngelo Dureghello <angelo@kernel-space.org>
Sat, 15 Apr 2023 19:36:07 +0000 (21:36 +0200)
There is an existing CONFIG_MCFTMR Kconfig symbol,
use it and drop all other instances of CFG_MCFTMR.
This duality is likely a result of bogus conversion
to Kconfig.

Fixes: 7ff7b46e6ce ("m68k: rename CONFIG_MCFTMR to CFG_MCFTMR")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
24 files changed:
arch/m68k/Kconfig
arch/m68k/cpu/mcf523x/interrupts.c
arch/m68k/cpu/mcf52x2/interrupts.c
arch/m68k/cpu/mcf532x/interrupts.c
arch/m68k/cpu/mcf5445x/interrupts.c
arch/m68k/include/asm/immap.h
arch/m68k/lib/time.c
board/freescale/m53017evb/README
board/freescale/m5373evb/README
include/configs/M5208EVBE.h
include/configs/M5235EVB.h
include/configs/M5249EVB.h
include/configs/M5253DEMO.h
include/configs/M5272C3.h
include/configs/M5275EVB.h
include/configs/M5282EVB.h
include/configs/M53017EVB.h
include/configs/M5329EVB.h
include/configs/M5373EVB.h
include/configs/amcore.h
include/configs/astro_mcf5373l.h
include/configs/cobra5272.h
include/configs/eb_cpu5282.h
include/configs/stmark2.h

index 76233ef563fb28b170d03186dd707445121b3d90..32759cde47d9bca7159b4b7cbd46748a09566d76 100644 (file)
@@ -200,5 +200,6 @@ source "board/sysam/stmark2/Kconfig"
 
 config MCFTMR
        bool "Use DMA timer"
+       default y
 
 endmenu
index b02ea29f635e034ffc9b5d2c630526f0396f822a..09c7f9e67cc79f0acd60773c48767c3fdc11f383 100644 (file)
@@ -22,7 +22,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
index e787c7605f8a8a8b3ba0ce9b40acd9359cb73e97..c5ed06007369710317b028a9030acbe019456e36 100644 (file)
@@ -34,7 +34,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
@@ -42,7 +42,7 @@ void dtimer_intr_setup(void)
        clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
        setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
 }
-#endif                         /* CFG_MCFTMR */
+#endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5272 */
 
 #if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
@@ -63,7 +63,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
@@ -72,7 +72,7 @@ void dtimer_intr_setup(void)
        clrbits_be32(&intp->imrl0, 0x00000001);
        clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
-#endif                         /* CFG_MCFTMR */
+#endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@@ -83,11 +83,11 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
        mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
 }
-#endif                         /* CFG_MCFTMR */
+#endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5249 || CONFIG_M5253 */
index bbe823c0cf7eb4e42799b774aa4b8a4ae879889e..4f72fa88e58c3a5aacebb9f050dd70ba0df74259 100644 (file)
@@ -23,7 +23,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
index fb80a879c7edc58a915ba79c4d43e91606fbfa27..400f3dee879e0096838c6452316dbb333823e617 100644 (file)
@@ -26,7 +26,7 @@ int interrupt_init(void)
        return 0;
 }
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 void dtimer_intr_setup(void)
 {
        int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
index 74516cc6219920f59e02125d1527082bc51cb956..3b515fe2c65d3d95180036a89c8d4ebb14ee7131 100644 (file)
@@ -16,7 +16,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -38,7 +38,7 @@
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -63,7 +63,7 @@
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (mbar_readLong(MCFSIM_IPR))
@@ -86,7 +86,7 @@
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (mbar_readLong(MCFSIM_IPR))
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
 #define CFG_SYS_NUM_IRQS               (64)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_TMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_TMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
 #define CFG_SYS_NUM_IRQS               (192)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
 #define CFG_SYS_NUM_IRQS               (128)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR3)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
 #define CFG_SYS_NUM_IRQS             (64)
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE          (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE             (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile intctrl_t *) \
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
 #define CFG_SYS_UART_BASE              (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG             (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
 #define MMAP_DSPI                      MMAP_DSPI0
 
 /* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
 #define CFG_SYS_UDELAY_BASE            (MMAP_DTMR0)
 #define CFG_SYS_TMR_BASE               (MMAP_DTMR1)
 #define CFG_SYS_TMRPND_REG     (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
index ca8c0396235350836209d9b11f5d370df3ff45a5..500e4dbbba2baec47a7296a042a549b0ceec390b 100644 (file)
@@ -25,7 +25,7 @@ static volatile ulong timestamp = 0;
 #define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
 #endif
 
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
 #ifndef CFG_SYS_UDELAY_BASE
 #      error   "uDelay base not defined!"
 #endif
@@ -111,7 +111,7 @@ ulong get_timer(ulong base)
        return (timestamp - base);
 }
 
-#endif                         /* CFG_MCFTMR */
+#endif                         /* CONFIG_MCFTMR */
 
 /*
  * This function is derived from PowerPC code (read timebase as long long).
index 5d5c5e7adf9702776349c7a0ad16b2e47c6361d8..34f05f3fdc7239a572f56a0d22cbec0bfa358af2 100644 (file)
@@ -87,7 +87,7 @@ CONFIG_SYS_FEC0_PINMUX                -- Set FEC0 Pin configuration
 CONFIG_SYS_FEC0_MIIBASE                -- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP               -- set FEC timeout loop
 
-CFG_MCFTMR                     -- define to use DMA timer
+CONFIG_MCFTMR                  -- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL             -- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT            -- define for I2C bit-banged
index e8bf75f4fb99670aa4e6576c84abf3b414487256..7240648796b5e48d80b1e1cbec906ee80f7a77c0 100644 (file)
@@ -86,7 +86,7 @@ CONFIG_SYS_FEC0_PINMUX                -- Set FEC0 Pin configuration
 CONFIG_SYS_FEC0_MIIBASE        -- Set FEC0 MII base register
 MCFFEC_TOUT_LOOP       -- set FEC timeout loop
 
-CFG_MCFTMR             -- define to use DMA timer
+CONFIG_MCFTMR          -- define to use DMA timer
 
 CONFIG_SYS_I2C_FSL     -- define to use FSL common I2C driver
 CONFIG_SYS_I2C_SOFT    -- define for I2C bit-banged
index 4b89f31209a4e19e4ea23915d4c0cc075f9bdc11..d4c1e0668845cf784062f1df356b2b94b477fa33 100644 (file)
 #define CFG_SYS_CS0_MASK               0x007F0001
 #define CFG_SYS_CS0_CTRL               0x00001FA0
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5208EVBE_H */
index 14d46178116bd1420f8b7af437a1c0bd5da2aec8..e54281834007abe88ff459313b747e9533b15b8f 100644 (file)
 #      define CFG_SYS_CS0_CTRL 0x00001D80
 #endif
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5329EVB_H */
index b24042328d330b1633e4d1f467736e2f08752520..2f4743ce50cf7dbd6bc4427b0ccf867af3c823d6 100644 (file)
 #define        CFG_SYS_GPIO1_OUT               0x00c70000      /* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED              0x00400000      /* user led                     */
 
-#define CFG_MCFTMR
 
 #endif /* M5249 */
index 008c7257c4328c9e5b47a2cb99d1160c63671b12..0ff0bfce90b09f9cd9b228d2d3d1e56fcede94d8 100644 (file)
 #define CFG_SYS_GPIO1_OUT              0x00c70000      /* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED              0x00400000      /* user led */
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5253DEMO_H */
index 49cf3e878eaca6e339b51cc9a8771781633209ae..98a17181a41efead383c8d91b461b166c6ea9e56 100644 (file)
 #define CFG_SYS_PBDAT          0x0000
 #define CFG_SYS_PDCNT          0x00000000
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5272C3_H */
index 965327d759de2cf48bd80c7e4636ac738c29015a..77ddf717643304655e2b8fff934890583ce5b399 100644 (file)
 #define CFG_SYS_CS1_CTRL               0x00001900
 #define CFG_SYS_CS1_MASK               0x00070001
 
-#define CFG_MCFTMR
 
 #endif /* _M5275EVB_H */
index f04d9b1b2abfa6b840261cdf29a70ef1a9103b09..e289a23b8008ee4c8e8f39984c6f688114e1e499 100644 (file)
 #define CFG_SYS_DDRUA          0x05
 #define CFG_SYS_PJPAR          0xFF
 
-#define CFG_MCFTMR
 
 #endif                         /* _CONFIG_M5282EVB_H */
index 04c456ff9f1577b61f8bc2db7ac0cdd32e01620b..dcc5701ee0bcd4521d8b2450fb4515b527644782 100644 (file)
 #define CFG_SYS_CS1_MASK               0x00070001
 #define CFG_SYS_CS1_CTRL               0x00001FA0
 
-#define CFG_MCFTMR
 
 #endif                         /* _M53017EVB_H */
index 0aa1ffd4d4faac79bb51a4b8b3c783404c6d5084..dd5d4c980233099e12e60ae87f1cad4acb14499d 100644 (file)
 #define CFG_SYS_CS2_CTRL               0x00001f60
 #endif
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5329EVB_H */
index 8b9e65de98c1924b0ef9d77d2d935d0df5f14ba2..4bb99487509fa939b912648078bac40ebe9da0ed 100644 (file)
 #define CFG_SYS_CS2_MASK               (16 << 20)
 #define CFG_SYS_CS2_CTRL               0x00001f60
 
-#define CFG_MCFTMR
 
 #endif                         /* _M5373EVB_H */
index ca8d17bfd2ce282c631396445b3cdec12fbc40d8..4c695fb9df99f05df34887307d7d9f7cd8302bf3 100644 (file)
@@ -10,7 +10,6 @@
 
 #define CFG_SYS_UART_PORT              0
 
-#define CFG_MCFTMR
 #define CFG_SYS_UART_PORT              0
 #define CFG_SYS_BAUDRATE_TABLE         { 9600, 19200, 38400, 57600, 115200 }
 
index 80f8c4129f581b8dee233e8b1ebd90d0e2d488bd..f3bfefa835e4d6e58a054d0a1f4beffbcc693428 100644 (file)
 #define CFG_SYS_CACHE_ICACR            (CF_CACR_EC | CF_CACR_CINVA | \
                                         CF_CACR_DCM_P)
 
-#define CFG_MCFTMR
 
 #endif /* _CONFIG_ASTRO_MCF5373L_H */
index 276ecc30ccc7c15df28f7895ec251fb88b2e75b0..556705fb09f7894c52275ea27438474932fad959 100644 (file)
@@ -184,6 +184,5 @@ configuration */
 #define CFG_SYS_PBDAT          0x0000                  /* PortB value reg. */
 #define CFG_SYS_PDCNT          0x00000000              /* PortD control reg. */
 
-#define CFG_MCFTMR
 
 #endif /* _CONFIG_COBRA5272_H */
index 9503ab66f0ff3afa93d84b1ca251df53b8629ea4..e2c9d9c43cee579f60bf400452bf8cd646a12814 100644 (file)
 #define CFG_SYS_DDRUA          0x05
 #define CFG_SYS_PJPAR          0xFF
 
-#define CFG_MCFTMR
 
 #endif /* _CONFIG_M5282EVB_H */
 /*---------------------------------------------------------------------*/
index 6edaf73d61b87d7c10b7900f91b7c220a1dffd72..af5da096b7d3767c4fd6f4f1295a0b7fc143ab4b 100644 (file)
@@ -95,7 +95,6 @@
 #define CACR_STATUS                    (CFG_SYS_INIT_RAM_ADDR + \
                                        CFG_SYS_INIT_RAM_SIZE - 12)
 
-#define CFG_MCFTMR
 
 #define CFG_SYS_I2C_0