/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/*
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
/*
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
/*
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#define CONFIG_DDR_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
/* ethernet */
#define CONFIG_SYS_RX_ETH_BUFFER 8
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
*/
#ifndef __LS1012A2G5RDB_H__
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __LS1012AFRWY_H__
func(DHCP, dhcp, na)
#endif
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#ifndef __LS1012AQDS_H__
DSPI_CTAR_DT(0))
#define CONFIG_SPI_FLASH_EON /* cs3 */
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor, Inc.
*/
#define __PHY_ETH2_MASK 0xFB
#define __PHY_ETH1_MASK 0xFD
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
-
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#ifndef __L1028A_COMMON_H
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
#define OCRAM_NONSECURE_SIZE 0x00010000
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015 Freescale Semiconductor
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#ifndef __LS1043A_COMMON_H
#endif
#endif
-/* MMC */
-#ifndef SPL_NO_MMC
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-#endif
-
/* DSPI */
#ifndef SPL_NO_DSPI
#ifdef CONFIG_FSL_DSPI
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#ifndef __LS1046A_COMMON_H
CONFIG_SYS_SCSI_MAX_LUN)
#endif
-/* MMC */
-#ifndef SPL_NO_MMC
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-#endif
-
/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017, 2020 NXP
+ * Copyright 2017, 2020-2021 NXP
*/
#ifndef __LS1088A_QDS_H
#define CONFIG_FSL_MEMAC
/* MMC */
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017, 2020 NXP
+ * Copyright 2017, 2020-2021 NXP
*/
#ifndef __LS1088A_RDB_H
#endif
#endif
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
#ifndef SPL_NO_ENV
#define BOOT_TARGET_DEVICES(func) \
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017, 2019-2020 NXP
+ * Copyright 2017, 2019-2021 NXP
* Copyright 2015 Freescale Semiconductor
*/
#define CONFIG_PCI_SCAN_SHOW
#endif
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017, 2019-2020 NXP
+ * Copyright 2017, 2019-2021 NXP
* Copyright 2015 Freescale Semiconductor
*/
#define CONFIG_PCI_SCAN_SHOW
#endif
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*/
#ifndef __LX2_COMMON_H
#define CONFIG_PCI_SCAN_SHOW
#endif
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
/* SATA */
#ifdef CONFIG_SCSI
CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
CONFIG_SYS_FSL_MC_BASE
CONFIG_SYS_FSL_MC_SIZE
-CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
CONFIG_SYS_FSL_NI_BASE
CONFIG_SYS_FSL_NI_SIZE
CONFIG_SYS_FSL_NO_SERDES