arm64: zynqmp: Writing correct value to ANALOG_BUS

The default register configuration after powerup for PSSYSMON_ANALOG_BUS
register is incorrect. Hence, fix this in SPL by writing correct fixed
value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit
sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c")
in Xilinx:embeddedsw[1].

[1] https://github.com/Xilinx/embeddedsw

Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index 3d3c48e24731238c5b2b3c71c579932e134426d1..a798aa0eb99cb54eeb6a2d80c7f6a8c5641b7166 100644 (file)
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -19,6 +19,11 @@
 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT      0
 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT     8
 
+#define ZYNQMP_AMS_PS_SYSMON_BASEADDR      0XFFA50800
+#define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \
+                                                           + 0x00000114)
+#define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210
+
 #define PS_MODE0       BIT(0)
 #define PS_MODE1       BIT(1)
 #define PS_MODE2       BIT(2)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index d05f0b2e120258b3e81f27d56515512b90e5e100..ee4d0c85e6b70800e27a99a5f04a0842f9f5409c 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -287,6 +287,17 @@ int board_early_init_f(void)
        if (ret)
                return ret;
 
+       /*
+        * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
+        * supply sense channel to SysMon supply registers inside the IP.
+        * This register must be programmed to complete SysMon IP
+        * configuration. The default register configuration after
+        * power-up is incorrect. Hence, fix this by writing the
+        * correct value - 0x3210.
+        */
+       writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
+              ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
+
        /* Delay is required for clocks to be propagated */
        udelay(1000000);
 #endif