arm: histb: hi3798mv200: add initial support for Hi3798MV200 HC2910-2AGHD05 board

A board with Hi3798MV200 SoC and various peripherals. Details are in the
board README.md.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>

diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi
new file mode 100644 (file)
index 0000000..eb32076
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "hi3798mv200-u-boot.dtsi"
+
+/* The clock driver is missing */
+&sd0 {
+       status = "disabled";
+};

diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts
new file mode 100644 (file)
index 0000000..c4ca5ed
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS File for Skyworth HC2910 with board label 2AGHD05 set-top box.
+ *
+ * Released under the GPLv2 only.
+ */
+
+/dts-v1/;
+
+#include "hi3798mv200.dtsi"
+
+/ {
+       // Usually known as Henan Guangdian HC2910
+       model = "Skyworth HC2910 with board label 2AGHD05";
+       compatible = "skyworth,hc2910-2aghd05", "hisilicon,hi3798mv200";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+};
+
+&ehci {
+       status = "okay";
+};
+
+&emmc {
+       fifo-depth = <256>;
+       clock-frequency = <200000000>;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       non-removable;
+       bus-width = <8>;
+       status = "okay";
+};
+
+&gmac {
+       status = "okay";
+       #address-cells = <1>;
+       #size-cells = <0>;
+       phy-handle = <&eth_phy1>;
+       phy-mode = "rgmii";
+       hisilicon,phy-reset-delays-us = <10000 10000 30000>;
+
+       eth_phy1: phy@3 {
+               reg = <3>;
+       };
+};
+
+&ohci {
+       status = "okay";
+};
+
+&sd0 {
+       bus-width = <4>;
+       cap-sd-highspeed;
+       status = "okay";
+};
+
+&uart0 {
+       status = "okay";
+};

diff --git a/arch/arm/dts/hi3798mv200-u-boot.dtsi b/arch/arm/dts/hi3798mv200-u-boot.dtsi
new file mode 100644 (file)
index 0000000..8917bcf
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to:
+ *  1) use platform data for the console
+ *
+ */
+
+#include <dt-bindings/reset/ti-syscon.h>
+
+/* The driver in U-Boot does not support "snps,dw-mshc" compatible. */
+&sd0 {
+       compatible = "hisilicon,hi3798mv200-dw-mshc";
+};
+
+&sd1 {
+       compatible = "hisilicon,hi3798mv200-dw-mshc";
+};
+
+/* The clock driver is missing */
+&uart0 {
+       clock = <75000000>;
+};

diff --git a/arch/arm/dts/hi3798mv200.dtsi b/arch/arm/dts/hi3798mv200.dtsi
new file mode 100644 (file)
index 0000000..fedf87a
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200.dtsi
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS File for HiSilicon Hi3798mv200 SoC.
+ *
+ * Released under the GPLv2 only.
+ */
+
+#include <dt-bindings/clock/histb-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+       compatible = "hisilicon,hi3798mv200";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0 0x0>;
+                       enable-method = "psci";
+               };
+
+               cpu@1 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0 0x1>;
+                       enable-method = "psci";
+               };
+
+               cpu@2 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0 0x2>;
+                       enable-method = "psci";
+               };
+
+               cpu@3 {
+                       compatible = "arm,cortex-a53";
+                       device_type = "cpu";
+                       reg = <0x0 0x3>;
+                       enable-method = "psci";
+               };
+       };
+
+       gic: interrupt-controller@f1001000 {
+               compatible = "arm,gic-400";
+               reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
+                     <0x0 0xf1002000 0x0 0x100>;   /* GICC */
+               #address-cells = <0>;
+               #interrupt-cells = <3>;
+               interrupt-controller;
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+                             IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       /* Initialization is done in boot loader */
+       usb2_phy1: hsusb1_phy {
+               compatible = "usb-nop-xceiv";
+               clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+               clock-names = "main";
+               #phy-cells = <0>;
+       };
+
+       soc: soc@f0000000 {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0xf0000000 0x10000000>;
+
+               crg: clock-reset-controller@8a22000 {
+                       compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd";
+                       reg = <0x8a22000 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <2>;
+               };
+
+               sysctrl: system-controller@8000000 {
+                       compatible = "hisilicon,hi3798mv200-sysctrl", "syscon";
+                       reg = <0x8000000 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <2>;
+               };
+
+               perictrl: peripheral-controller@8a20000 {
+                       compatible = "hisilicon,hi3798mv200-perictrl", "syscon",
+                                    "simple-mfd";
+                       reg = <0x8a20000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x8a20000 0x1000>;
+
+                       combphy0: phy@850 {
+                               compatible = "hisilicon,hi3798mv200-combphy";
+                               reg = <0x850 0x8>;
+                               #phy-cells = <1>;
+                               clocks = <&crg HISTB_COMBPHY0_CLK>;
+                               resets = <&crg 0x188 4>;
+                               assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
+                               assigned-clock-rates = <100000000>;
+                               hisilicon,fixed-mode = <PHY_TYPE_USB3>;
+                       };
+               };
+
+               pmx0: pinconf@8a21000 {
+                       compatible = "pinconf-single";
+                       reg = <0x8a21000 0x180>;
+                       pinctrl-single,register-width = <32>;
+                       pinctrl-single,function-mask = <7>;
+               };
+
+               uart0: serial@8b00000 {
+                       compatible = "arm,pl011", "arm,primecell";
+                       reg = <0x8b00000 0x1000>;
+                       interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sysctrl HISTB_UART0_CLK>;
+                       clock-names = "apb_pclk";
+                       status = "disabled";
+               };
+
+               sd0: mmc@9820000 {
+                       compatible = "snps,dw-mshc";
+                       reg = <0x9820000 0x10000>;
+                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_SDIO0_CIU_CLK>,
+                                <&crg HISTB_SDIO0_BIU_CLK>;
+                       clock-names = "ciu", "biu";
+                       resets = <&crg 0x9c 4>;
+                       reset-names = "reset";
+                       status = "disabled";
+               };
+
+               emmc: mmc@9830000 {
+                       compatible = "hisilicon,hi3798mv200-dw-mshc";
+                       reg = <0x9830000 0x10000>;
+                       interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_MMC_CIU_CLK>,
+                                <&crg HISTB_MMC_BIU_CLK>,
+                                <&crg HISTB_MMC_SAMPLE_CLK>,
+                                <&crg HISTB_MMC_DRV_CLK>;
+                       clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+                       resets = <&crg 0xa0 4>;
+                       reset-names = "reset";
+                       status = "disabled";
+               };
+
+               gmac: ethernet@9840000 {
+                       compatible = "hisilicon,hi3798mv200-gmac", "hisilicon,hisi-gmac-v2";
+                       reg = <0x9840000 0x1000>,
+                             <0x984300c 0x4>;
+                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_ETH0_MAC_CLK>,
+                                <&crg HISTB_ETH0_MACIF_CLK>;
+                       clock-names = "mac_core", "mac_ifc";
+                       resets = <&crg 0xcc 0>,
+                                <&crg 0xcc 2>,
+                                <&crg 0xcc 5>;
+                       reset-names = "mac_core", "mac_ifc", "phy";
+                       status = "disabled";
+               };
+
+               ohci: ohci@9880000 {
+                       compatible = "generic-ohci";
+                       reg = <0x9880000 0x10000>;
+                       interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_USB2_BUS_CLK>,
+                                <&crg HISTB_USB2_12M_CLK>,
+                                <&crg HISTB_USB2_48M_CLK>;
+                       clock-names = "bus", "clk12", "clk48";
+                       resets = <&crg 0xb8 12>;
+                       reset-names = "bus";
+                       status = "disabled";
+               };
+
+               ehci: ehci@9890000 {
+                       compatible = "generic-ehci";
+                       reg = <0x9890000 0x10000>;
+                       interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_USB2_BUS_CLK>,
+                                <&crg HISTB_USB2_PHY_CLK>,
+                                <&crg HISTB_USB2_UTMI_CLK>;
+                       clock-names = "bus", "phy", "utmi";
+                       resets = <&crg 0xb8 12>,
+                                <&crg 0xb8 16>,
+                                <&crg 0xb8 13>;
+                       reset-names = "bus", "phy", "utmi";
+                       phys = <&usb2_phy1>;
+                       phy-names = "usb";
+                       status = "disabled";
+               };
+
+               sd1: mmc@9c40000 {
+                       compatible = "snps,dw-mshc";
+                       reg = <0x9c40000 0x10000>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&crg HISTB_SDIO1_CIU_CLK>,
+                                <&crg HISTB_SDIO1_BIU_CLK>;
+                       clock-names = "ciu", "biu";
+                       resets = <&crg 0x28c 4>;
+                       reset-names = "reset";
+                       status = "disabled";
+               };
+       };
+};

diff --git a/arch/arm/mach-histb/Kconfig b/arch/arm/mach-histb/Kconfig
index 78d40859a307f0c86e817b3e0f53942dbd2d2fec..012dbfe8bc6f5bf3eff9d5323aed75333e8881cb 100644 (file)
--- a/arch/arm/mach-histb/Kconfig
+++ b/arch/arm/mach-histb/Kconfig
@@ -11,4 +11,29 @@ config ARCH_HI3798MV2X
 
 endchoice
 
+if ARCH_HI3798MV2X
+
+choice
+       prompt "Select a Hi3798M V2XX based board"
+
+config TARGET_HC2910_2AGHD05
+       bool "Skyworth HC2910 with board label 2AGHD05"
+       help
+         Support for Skyworth HC2910 with board label 2AGHD05. This board features:
+         - Hisilicon Hi3798MV200 SoC (4xCortex-A53, Mali MP-450)
+         - 2GiB DRAM
+         - 8GiB eMMC, uSD slot
+         - Wifi and Bluetooth module
+         - 1x USB 2.0, 1x USB 3.0 host port
+         - HDMI
+         - SCI
+         - 3 LED - power, Wifi, Lock(?)
+         - 1x Fast Ethernet Controller, 1x GBe Ethernet Controller
+
+endchoice
+
+endif
+
+source "board/skyworth/hc2910-2aghd05/Kconfig"
+
 endif

diff --git a/board/skyworth/hc2910-2aghd05/Kconfig b/board/skyworth/hc2910-2aghd05/Kconfig
new file mode 100644 (file)
index 0000000..f85f1f2
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HC2910_2AGHD05
+
+config SYS_BOARD
+       default "hc2910-2aghd05"
+
+config SYS_VENDOR
+       default "skyworth"
+
+config SYS_SOC
+       default "hi3798mv200"
+
+config SYS_CONFIG_NAME
+       default "hc2910-2aghd05"
+
+endif

diff --git a/board/skyworth/hc2910-2aghd05/MAINTAINERS b/board/skyworth/hc2910-2aghd05/MAINTAINERS
new file mode 100644 (file)
index 0000000..2c1e750
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/MAINTAINERS
@@ -0,0 +1,6 @@
+HC2910 2AGHD05 BOARD
+M: Yang Xiwen <firbidden405@outlook.com>
+S: Maintained
+F: board/skyworth/hc2910-2aghd05
+F: include/configs/hc2910-2aghd05.h
+F: configs/hc2910_2aghd05_defconfig

diff --git a/board/skyworth/hc2910-2aghd05/Makefile b/board/skyworth/hc2910-2aghd05/Makefile
new file mode 100644 (file)
index 0000000..193fd15
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/Makefile
@@ -0,0 +1 @@
+obj-y  := hc2910-2aghd05.o

diff --git a/board/skyworth/hc2910-2aghd05/README b/board/skyworth/hc2910-2aghd05/README
new file mode 100644 (file)
index 0000000..a838956
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/README
@@ -0,0 +1,25 @@
+================================================================================
+                       Board Information
+================================================================================
+
+The board features the Hi3798M V200 with an integrated quad-core 64-bit ARM
+Cortex A53 processor.
+SOC  Hisilicon Hi3798CV200
+CPU  Quad-core ARM Cortex-A53 64 bit
+DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
+USB  1x USB 2.0 ports 1x USB 3.0 ports
+CONSOLE  USB-micro port for console support
+ETHERNET  1 GBe Ethernet, 1 MBe Ethernet
+WIFI  802.11n with Bluebooth
+CONNECTORS  One connector for Smart Card One connector for TSI
+
+
+================================================================================
+                       BUILD INSTRUCTIONS
+================================================================================
+
+The U-Boot relies on a modified l-loader and TF-A for Hi3798MV200.
+The source for l-loader can be obtained at: [l-loader](https://github.com/185264646/l-loader)
+The mainline port for TF-A is still under development. For now, you can use the TF-A for poplar directly.
+
+For more information, please refer to <board/hisilicon/poplar/README>.

diff --git a/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c
new file mode 100644 (file)
index 0000000..abad5ef
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for Skyworth HC2910 2AGHD05
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/system.h>
+#include <linux/io.h>
+
+#define HI3798MV200_PERI_CTRL_BASE 0xf8a20000
+#define SDIO0_LDO_OFFSET 0x11c
+
+static int sdio0_set_ldo(void)
+{
+       // SDIO LDO bypassed, 3.3V
+       writel(HI3798MV200_PERI_CTRL_BASE + SDIO0_LDO_OFFSET, 0x60);
+       return 0;
+}
+
+int board_init(void)
+{
+       sdio0_set_ldo();
+       return 0;
+}

diff --git a/configs/hc2910_2aghd05_defconfig b/configs/hc2910_2aghd05_defconfig
new file mode 100644 (file)
index 0000000..dfd3e65
--- /dev/null
+++ b/configs/hc2910_2aghd05_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_HISTB=y
+CONFIG_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x1F0000
+CONFIG_DEFAULT_DEVICE_TREE="hi3798mv200-hc2910-2aghd05"
+CONFIG_SYS_PROMPT="HC2910# "
+CONFIG_IDENT_STRING="HC2910"
+CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_EXPERT is not set
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=537
+CONFIG_CMD_BOOTDEV=y
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_NVEDIT_INFO=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+# CONFIG_GPIO is not set
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_K3=y
+# CONFIG_POWER is not set
+CONFIG_FS_BTRFS=y
+CONFIG_FAT_WRITE=y
+CONFIG_REGEX=y
+# CONFIG_EFI_LOADER is not set

diff --git a/include/configs/hc2910-2aghd05.h b/include/configs/hc2910-2aghd05.h
new file mode 100644 (file)
index 0000000..3db9a47
--- /dev/null
+++ b/include/configs/hc2910-2aghd05.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __HC2910_2AGHD05_CONFIG_H__
+#define __HC2910_2AGHD05_CONFIG_H__
+
+#endif