]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: socfpga: Convert Arria10 to timer framework
authorMarek Vasut <marex@denx.de>
Sat, 18 Aug 2018 14:00:31 +0000 (16:00 +0200)
committerMarek Vasut <marex@denx.de>
Fri, 24 Aug 2018 10:05:20 +0000 (12:05 +0200)
Switch the Arria10 from ad-hoc hardcoded timer to timer framework
and the DW APB timer driver. This allows the A10 to extract timer
information, like timer rate, from clock framework and thus DT
instead of having it hardcoded in U-Boot configuration files.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
arch/arm/mach-socfpga/Makefile
configs/socfpga_arria10_defconfig
include/configs/socfpga_common.h

index 654999cdf680eef370a278d60a3658c7f1caf040..e66720447f85e22d9c4c97f6ffb24e005e09dc37 100644 (file)
@@ -26,7 +26,6 @@ obj-y += clock_manager_arria10.o
 obj-y  += misc_arria10.o
 obj-y  += pinmux_arria10.o
 obj-y  += reset_manager_arria10.o
-obj-y  += timer.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
index 4b0d47489aa0f818a296cda44ae50459983e058e..a5040355476db333edd51b18e143a07520242b09 100644 (file)
@@ -39,4 +39,7 @@ CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
 CONFIG_USE_TINY_PRINTF=y
index 440a918fc7c8b00b30701280eb0765a58348d510..2330143cf1ce40ebba7d30c8d19ea7f8c5cb790f 100644 (file)
 /*
  * L4 OSC1 Timer 0
  */
+#ifndef CONFIG_TIMER
 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMERBASE + 0x4)
 #define CONFIG_SYS_TIMER_RATE          25000000
+#endif
 
 /*
  * L4 Watchdog