ARM: imx: Update DRAM timings with inline ECC on DH i.MX8MP DHCOM SoM

Import DRAM timings generated by the DDR tool 3.31 which introduce assorted
tweaks to the DRAM controller settings. Furthermore, enable DBI to improve
noise resilience of the DRAM bus by reducing the number of bit changes on
the bus.

Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors
reported by EDAC . It is not entirely clear why the slightly faster setting
does produce sporadic correctable errors, while this one does not, but this
could be related to simpler PLL setting at 3600 MTps.

Enable inline ECC which is necessary to detect ECC errors and collect
statistics by the EDAC driver in Linux. This reduces the DRAM size by
64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available
DRAM size becomes 3.5 GiB and for 2 GiB device the available DRAM size
becomes 1.8 GiB.

Signed-off-by: Marek Vasut <marex@denx.de>

diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 5edb85e1de53376e5dedae54d4f16966f73d7418..5f12d787d3835a644399b983cc87d881f78717d5 100644 (file)
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <dm.h>
@@ -30,9 +31,11 @@ int mach_cpu_init(void)
 int board_phys_sdram_size(phys_size_t *size)
 {
        const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
+       const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
        u8 memcfg = dh_get_memcfg();
 
-       *size = (u64)memsz[memcfg] << 20ULL;
+       /* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */
+       *size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0));
 
        return 0;
 }

diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
index 7894da3b91841ca6e91b9e36d0b965bcab7f9be9..c4d51174a33f979fd8c547edc948d0daf8b5a999 100644 (file)
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
@@ -9,6 +9,12 @@
 extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
 extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
 
+typedef void (*scrub_func_t)(void);
+extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);
+extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);
+
 u8 dh_get_memcfg(void);
 
+#define DDRC_ECCCFG0_ECC_MODE_MASK     0x7
+
 #endif /* __LPDDR4_TIMING_H__ */

diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
index 51b8c4cf7ba9c9626df4ba9ab31f4c1fff74d90e..add7a0bf23b2c65358107a5200cd8ecf5d3e52f5 100644 (file)
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
@@ -14,48 +14,62 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d400030, 0x1 },
        { 0x3d400000, 0xa1080020 },
        { 0x3d400020, 0x1323 },
-       { 0x3d400024, 0x1c79100 },
-       { 0x3d400064, 0x710106 },
+       { 0x3d400024, 0x1b77400 },
+       { 0x3d400064, 0x6d00fc },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d400070, 0x7027fd4 },
+#else
        { 0x3d400070, 0x7027f90 },
+#endif
        { 0x3d400074, 0x790 },
-       { 0x3d4000d0, 0xc0030720 },
-       { 0x3d4000d4, 0xb80000 },
+       { 0x3d4000d0, 0xc00306df },
+       { 0x3d4000d4, 0xb10000 },
        { 0x3d4000dc, 0xe40036 },
-       { 0x3d4000e0, 0x330000 },
+       { 0x3d4000e0, 0xf30000 },
        { 0x3d4000e8, 0x660048 },
        { 0x3d4000ec, 0x160048 },
-       { 0x3d400100, 0x1e262028 },
-       { 0x3d400104, 0x7073b },
-       { 0x3d40010c, 0xe0e000 },
-       { 0x3d400110, 0x11040a11 },
+       { 0x3d400100, 0x1d241e26 },
+       { 0x3d400104, 0x70739 },
+       { 0x3d40010c, 0xd0d000 },
+       { 0x3d400110, 0x11040911 },
        { 0x3d400114, 0x2050e0e },
        { 0x3d400118, 0x1010008 },
        { 0x3d40011c, 0x502 },
        { 0x3d400130, 0x20700 },
        { 0x3d400134, 0xd100002 },
-       { 0x3d400138, 0x10d },
-       { 0x3d400144, 0xbb005e },
-       { 0x3d400180, 0x3a5001c },
-       { 0x3d400184, 0x2f071e5 },
+       { 0x3d400138, 0x103 },
+       { 0x3d400144, 0xb4005a },
+       { 0x3d400180, 0x384001b },
+       { 0x3d400184, 0x2d06ddd },
        { 0x3d400188, 0x0 },
-       { 0x3d400190, 0x49b820c },
+       { 0x3d400190, 0x49f820c },
        { 0x3d400194, 0x80303 },
-       { 0x3d4001b4, 0x1b0c },
+       { 0x3d4001b4, 0x1f0c },
        { 0x3d4001a0, 0xe0400018 },
        { 0x3d4001a4, 0xdf00e4 },
        { 0x3d4001a8, 0x80000000 },
        { 0x3d4001b0, 0x11 },
-       { 0x3d4001c0, 0x1 },
+       { 0x3d4001c0, 0x7 },
        { 0x3d4001c4, 0x1 },
        { 0x3d4000f4, 0x799 },
-       { 0x3d400108, 0x810191a },
+       { 0x3d400108, 0x8121b1a },
        { 0x3d400200, 0x1f },
        { 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d40020c, 0x13131300 },
+#else
        { 0x3d40020c, 0x0 },
+#endif
        { 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d400204, 0x50505 },
+       { 0x3d400214, 0x4040404 },
+       { 0x3d400218, 0x4040404 },
+#else
        { 0x3d400204, 0x80808 },
        { 0x3d400214, 0x7070707 },
        { 0x3d400218, 0x7070707 },
+#endif
        { 0x3d40021c, 0xf0f },
        { 0x3d400250, 0x1705 },
        { 0x3d400254, 0x2c },
@@ -74,7 +88,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402050, 0x20d000 },
        { 0x3d402064, 0xc001c },
        { 0x3d4020dc, 0x840000 },
-       { 0x3d4020e0, 0x330000 },
+       { 0x3d4020e0, 0xf30000 },
        { 0x3d4020e8, 0x660048 },
        { 0x3d4020ec, 0x160048 },
        { 0x3d402100, 0xa040305 },
@@ -99,7 +113,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d403050, 0x20d000 },
        { 0x3d403064, 0x30007 },
        { 0x3d4030dc, 0x840000 },
-       { 0x3d4030e0, 0x330000 },
+       { 0x3d4030e0, 0xf30000 },
        { 0x3d4030e8, 0x660048 },
        { 0x3d4030ec, 0x160048 },
        { 0x3d403100, 0xa010102 },
@@ -269,7 +283,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
        { 0x20018, 0x3 },
        { 0x20075, 0x4 },
        { 0x20050, 0x0 },
-       { 0x20008, 0x3a5 },
+       { 0x20008, 0x384 },
        { 0x120008, 0x64 },
        { 0x220008, 0x19 },
        { 0x20088, 0x9 },
@@ -315,19 +329,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
        { 0x200f6, 0x0 },
        { 0x200f7, 0xf000 },
        { 0x20025, 0x0 },
-       { 0x2002d, 0x0 },
-       { 0x12002d, 0x0 },
-       { 0x22002d, 0x0 },
+       { 0x2002d, 0x1 },
+       { 0x12002d, 0x1 },
+       { 0x22002d, 0x1 },
        { 0x2007d, 0x212 },
        { 0x12007d, 0x212 },
        { 0x22007d, 0x212 },
        { 0x2007c, 0x61 },
        { 0x12007c, 0x61 },
        { 0x22007c, 0x61 },
-       { 0x1004a, 0x500 },
-       { 0x1104a, 0x500 },
-       { 0x1204a, 0x500 },
-       { 0x1304a, 0x500 },
        { 0x2002c, 0x0 },
 };
 
@@ -1057,7 +1067,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 /* P0 message block paremeter for training firmware */
 static struct dram_cfg_param ddr_fsp0_cfg[] = {
        { 0xd0000, 0x0 },
-       { 0x54003, 0xe94 },
+       { 0x54003, 0xe10 },
        { 0x54004, 0x2 },
        { 0x54005, 0x2228 },
        { 0x54006, 0x14 },
@@ -1067,25 +1077,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
        { 0x5400f, 0x100 },
        { 0x54012, 0x110 },
        { 0x54019, 0x36e4 },
-       { 0x5401a, 0x33 },
+       { 0x5401a, 0xf3 },
        { 0x5401b, 0x4866 },
        { 0x5401c, 0x4800 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x36e4 },
-       { 0x54020, 0x33 },
+       { 0x54020, 0xf3 },
        { 0x54021, 0x4866 },
        { 0x54022, 0x4800 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x1 },
        { 0x54032, 0xe400 },
-       { 0x54033, 0x3336 },
+       { 0x54033, 0xf336 },
        { 0x54034, 0x6600 },
        { 0x54035, 0x48 },
        { 0x54036, 0x48 },
        { 0x54037, 0x1600 },
        { 0x54038, 0xe400 },
-       { 0x54039, 0x3336 },
+       { 0x54039, 0xf336 },
        { 0x5403a, 0x6600 },
        { 0x5403b, 0x48 },
        { 0x5403c, 0x48 },
@@ -1107,25 +1117,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
        { 0x5400f, 0x100 },
        { 0x54012, 0x110 },
        { 0x54019, 0x84 },
-       { 0x5401a, 0x33 },
+       { 0x5401a, 0xf3 },
        { 0x5401b, 0x4866 },
        { 0x5401c, 0x4800 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x84 },
-       { 0x54020, 0x33 },
+       { 0x54020, 0xf3 },
        { 0x54021, 0x4866 },
        { 0x54022, 0x4800 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x1 },
        { 0x54032, 0x8400 },
-       { 0x54033, 0x3300 },
+       { 0x54033, 0xf300 },
        { 0x54034, 0x6600 },
        { 0x54035, 0x48 },
        { 0x54036, 0x48 },
        { 0x54037, 0x1600 },
        { 0x54038, 0x8400 },
-       { 0x54039, 0x3300 },
+       { 0x54039, 0xf300 },
        { 0x5403a, 0x6600 },
        { 0x5403b, 0x48 },
        { 0x5403c, 0x48 },
@@ -1147,25 +1157,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
        { 0x5400f, 0x100 },
        { 0x54012, 0x110 },
        { 0x54019, 0x84 },
-       { 0x5401a, 0x33 },
+       { 0x5401a, 0xf3 },
        { 0x5401b, 0x4866 },
        { 0x5401c, 0x4800 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x84 },
-       { 0x54020, 0x33 },
+       { 0x54020, 0xf3 },
        { 0x54021, 0x4866 },
        { 0x54022, 0x4800 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x1 },
        { 0x54032, 0x8400 },
-       { 0x54033, 0x3300 },
+       { 0x54033, 0xf300 },
        { 0x54034, 0x6600 },
        { 0x54035, 0x48 },
        { 0x54036, 0x48 },
        { 0x54037, 0x1600 },
        { 0x54038, 0x8400 },
-       { 0x54039, 0x3300 },
+       { 0x54039, 0xf300 },
        { 0x5403a, 0x6600 },
        { 0x5403b, 0x48 },
        { 0x5403c, 0x48 },
@@ -1176,7 +1186,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
 /* P0 2D message block paremeter for training firmware */
 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0xd0000, 0x0 },
-       { 0x54003, 0xe94 },
+       { 0x54003, 0xe10 },
        { 0x54004, 0x2 },
        { 0x54005, 0x2228 },
        { 0x54006, 0x14 },
@@ -1187,25 +1197,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54010, 0x1f7f },
        { 0x54012, 0x110 },
        { 0x54019, 0x36e4 },
-       { 0x5401a, 0x33 },
+       { 0x5401a, 0xf3 },
        { 0x5401b, 0x4866 },
        { 0x5401c, 0x4800 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x36e4 },
-       { 0x54020, 0x33 },
+       { 0x54020, 0xf3 },
        { 0x54021, 0x4866 },
        { 0x54022, 0x4800 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x1 },
        { 0x54032, 0xe400 },
-       { 0x54033, 0x3336 },
+       { 0x54033, 0xf336 },
        { 0x54034, 0x6600 },
        { 0x54035, 0x48 },
        { 0x54036, 0x48 },
        { 0x54037, 0x1600 },
        { 0x54038, 0xe400 },
-       { 0x54039, 0x3336 },
+       { 0x54039, 0xf336 },
        { 0x5403a, 0x6600 },
        { 0x5403b, 0x48 },
        { 0x5403c, 0x48 },
@@ -1695,9 +1705,9 @@ static struct dram_cfg_param ddr_phy_pie[] = {
        { 0x400d7, 0x20b },
        { 0x2003a, 0x2 },
        { 0x200be, 0x3 },
-       { 0x2000b, 0x419 },
-       { 0x2000c, 0xe9 },
-       { 0x2000d, 0x91c },
+       { 0x2000b, 0x3f4 },
+       { 0x2000c, 0xe1 },
+       { 0x2000d, 0x8ca },
        { 0x2000e, 0x2c },
        { 0x12000b, 0x70 },
        { 0x12000c, 0x19 },
@@ -1800,8 +1810,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 
 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
        {
-               /* P0 3733mts 1D */
-               .drate = 3733,
+               /* P0 3600mts 1D */
+               .drate = 3600,
                .fw_type = FW_1D_IMAGE,
                .fsp_cfg = ddr_fsp0_cfg,
                .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1821,8 +1831,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
                .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
        },
        {
-               /* P0 3733mts 2D */
-               .drate = 3733,
+               /* P0 3600mts 2D */
+               .drate = 3600,
                .fw_type = FW_2D_IMAGE,
                .fsp_cfg = ddr_fsp0_2d_cfg,
                .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1841,5 +1851,19 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32 = {
        .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
        .ddrphy_pie = ddr_phy_pie,
        .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-       .fsp_table = { 3733, 400, 100, },
+       .fsp_table = { 3600, 400, 100, },
 };
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void dh_imx8mp_dhcom_dram_scrub_16g_x32(void)
+{
+       ddrc_inline_ecc_scrub(0x0,0x3ffffff);
+       ddrc_inline_ecc_scrub(0x4000000,0x7ffffff);
+       ddrc_inline_ecc_scrub(0x8000000,0xbffffff);
+       ddrc_inline_ecc_scrub(0xc000000,0xfffffff);
+       ddrc_inline_ecc_scrub(0x10000000,0x13ffffff);
+       ddrc_inline_ecc_scrub(0x14000000,0x17ffffff);
+       ddrc_inline_ecc_scrub(0x18000000,0x1bffffff);
+       ddrc_inline_ecc_scrub_end(0x0,0x1fffffff);
+}
+#endif

diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
index a4c1b121c27408b0844fd308ad0d1f0a5f77eed9..41b078f6e9f6f2b1aaa4eec6fd7c64a2c5e94a0f 100644 (file)
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
@@ -14,47 +14,66 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d400030, 0x1 },
        { 0x3d400000, 0xa3080020 },
        { 0x3d400020, 0x1323 },
-       { 0x3d400024, 0x1c79100 },
-       { 0x3d400064, 0x710106 },
+       { 0x3d400024, 0x1b77400 },
+       { 0x3d400064, 0x6d00fc },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d400070, 0x7027fd4 },
+#else
        { 0x3d400070, 0x7027f90 },
+#endif
        { 0x3d400074, 0x790 },
-       { 0x3d4000d0, 0xc0030720 },
-       { 0x3d4000d4, 0xb80000 },
+       { 0x3d4000d0, 0xc00306df },
+       { 0x3d4000d4, 0xb10000 },
        { 0x3d4000dc, 0xe40036 },
-       { 0x3d4000e0, 0x330000 },
+       { 0x3d4000e0, 0xf30000 },
        { 0x3d4000e8, 0x660048 },
        { 0x3d4000ec, 0x160048 },
-       { 0x3d400100, 0x1e262028 },
-       { 0x3d400104, 0x7073b },
-       { 0x3d40010c, 0xe0e000 },
-       { 0x3d400110, 0x11040a11 },
+       { 0x3d400100, 0x1d241e26 },
+       { 0x3d400104, 0x70739 },
+       { 0x3d40010c, 0xd0d000 },
+       { 0x3d400110, 0x11040911 },
        { 0x3d400114, 0x2050e0e },
        { 0x3d400118, 0x1010008 },
-       { 0x3d40011c, 0x501 },
+       { 0x3d40011c, 0x502 },
        { 0x3d400130, 0x20700 },
-       { 0x3d400134, 0xe100002 },
-       { 0x3d400138, 0x10d },
-       { 0x3d400144, 0xbb005e },
-       { 0x3d400180, 0x3a5001c },
-       { 0x3d400184, 0x2f071e5 },
+       { 0x3d400134, 0xd100002 },
+       { 0x3d400138, 0x103 },
+       { 0x3d400144, 0xb4005a },
+       { 0x3d400180, 0x384001b },
+       { 0x3d400184, 0x2d06ddd },
        { 0x3d400188, 0x0 },
-       { 0x3d400190, 0x49b820c },
+       { 0x3d400190, 0x49f820c },
        { 0x3d400194, 0x80303 },
-       { 0x3d4001b4, 0x1b0c },
+       { 0x3d4001b4, 0x1f0c },
        { 0x3d4001a0, 0xe0400018 },
        { 0x3d4001a4, 0xdf00e4 },
        { 0x3d4001a8, 0x80000000 },
        { 0x3d4001b0, 0x11 },
-       { 0x3d4001c0, 0x1 },
+       { 0x3d4001c0, 0x7 },
        { 0x3d4001c4, 0x1 },
-       { 0x3d4000f4, 0xc99 },
-       { 0x3d400108, 0x810191a },
+       { 0x3d4000f4, 0x799 },
+       { 0x3d400108, 0x8121b1a },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d400200, 0x14 },
+#else
        { 0x3d400200, 0x17 },
+#endif
+       { 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d40020c, 0x14141400 },
+#else
        { 0x3d40020c, 0x0 },
+#endif
        { 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+       { 0x3d400204, 0x50505 },
+       { 0x3d400214, 0x4040404 },
+       { 0x3d400218, 0x4040404 },
+#else
        { 0x3d400204, 0x80808 },
        { 0x3d400214, 0x7070707 },
        { 0x3d400218, 0x7070707 },
+#endif
        { 0x3d40021c, 0xf0f },
        { 0x3d400250, 0x1705 },
        { 0x3d400254, 0x2c },
@@ -73,7 +92,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402050, 0x20d000 },
        { 0x3d402064, 0xc001c },
        { 0x3d4020dc, 0x840000 },
-       { 0x3d4020e0, 0x330000 },
+       { 0x3d4020e0, 0xf30000 },
        { 0x3d4020e8, 0x660048 },
        { 0x3d4020ec, 0x160048 },
        { 0x3d402100, 0xa040305 },
@@ -83,7 +102,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402110, 0x2040202 },
        { 0x3d402114, 0x2030202 },
        { 0x3d402118, 0x1010004 },
-       { 0x3d40211c, 0x301 },
+       { 0x3d40211c, 0x302 },
        { 0x3d402130, 0x20300 },
        { 0x3d402134, 0xa100002 },
        { 0x3d402138, 0x1d },
@@ -92,13 +111,13 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402190, 0x3818200 },
        { 0x3d402194, 0x80303 },
        { 0x3d4021b4, 0x100 },
-       { 0x3d4020f4, 0xc99 },
+       { 0x3d4020f4, 0x599 },
        { 0x3d403020, 0x1021 },
        { 0x3d403024, 0xc3500 },
        { 0x3d403050, 0x20d000 },
        { 0x3d403064, 0x30007 },
        { 0x3d4030dc, 0x840000 },
-       { 0x3d4030e0, 0x330000 },
+       { 0x3d4030e0, 0xf30000 },
        { 0x3d4030e8, 0x660048 },
        { 0x3d4030ec, 0x160048 },
        { 0x3d403100, 0xa010102 },
@@ -108,7 +127,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d403110, 0x2040202 },
        { 0x3d403114, 0x2030202 },
        { 0x3d403118, 0x1010004 },
-       { 0x3d40311c, 0x301 },
+       { 0x3d40311c, 0x302 },
        { 0x3d403130, 0x20300 },
        { 0x3d403134, 0xa100002 },
        { 0x3d403138, 0x8 },
@@ -117,7 +136,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d403190, 0x3818200 },
        { 0x3d403194, 0x80303 },
        { 0x3d4031b4, 0x100 },
-       { 0x3d4030f4, 0xc99 },
+       { 0x3d4030f4, 0x599 },
        { 0x3d400028, 0x0 },
 };
 
@@ -268,7 +287,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
        { 0x20018, 0x3 },
        { 0x20075, 0x4 },
        { 0x20050, 0x0 },
-       { 0x20008, 0x3a5 },
+       { 0x20008, 0x384 },
        { 0x120008, 0x64 },
        { 0x220008, 0x19 },
        { 0x20088, 0x9 },
@@ -314,19 +333,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
        { 0x200f6, 0x0 },
        { 0x200f7, 0xf000 },
        { 0x20025, 0x0 },
-       { 0x2002d, 0x0 },
-       { 0x12002d, 0x0 },
-       { 0x22002d, 0x0 },
+       { 0x2002d, 0x1 },
+       { 0x12002d, 0x1 },
+       { 0x22002d, 0x1 },
        { 0x2007d, 0x212 },
        { 0x12007d, 0x212 },
        { 0x22007d, 0x212 },
        { 0x2007c, 0x61 },
        { 0x12007c, 0x61 },
        { 0x22007c, 0x61 },
-       { 0x1004a, 0x500 },
-       { 0x1104a, 0x500 },
-       { 0x1204a, 0x500 },
-       { 0x1304a, 0x500 },
        { 0x2002c, 0x0 },
 };
 
@@ -1056,7 +1071,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
 /* P0 message block paremeter for training firmware */
 static struct dram_cfg_param ddr_fsp0_cfg[] = {
        { 0xd0000, 0x0 },
-       { 0x54003, 0xe94 },
+       { 0x54003, 0xe10 },
        { 0x54004, 0x2 },
        { 0x54005, 0x2228 },
        { 0x54006, 0x14 },
@@ -1066,25 +1081,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
        { 0x5400f, 0x100 },
        { 0x54012, 0x310 },
        { 0x54019, 0x36e4 },
-       { 0x5401a, 0x33 },
+       { 0x5401a, 0xf3 },
        { 0x5401b, 0x4866 },
        { 0x5401c, 0x4800 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x36e4 },
-       { 0x54020, 0x33 },
+       { 0x54020, 0xf3 },
        { 0x54021, 0x4866 },
        { 0x54022, 0x4800 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x3 },
        { 0x54032, 0xe400 },
-       { 0x54033, 0x3336 },
+       { 0x54033, 0xf336 },
        { 0x54034, 0x6600 },
        { 0x54035, 0x48 },
        { 0x54036, 0x48 },
        { 0x54037, 0x1600 },
        { 0x54038, 0xe400 },
-       { 0x54039, 0x3336 },
+       { 0x54039, 0xf336 },
        { 0x5403a, 0x6600 },
        { 0x5403b, 0x48 },
        { 0x5403c, 0x48 },
@@ -1106,25 +1121,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
        { 0x5400f, 0x100 },
        { 0x54012, 0x310 },
        { 0x54019, 0x84 },
-       { 0x5401a, 0x33 },
+       { 0x5401a, 0xf3 },
        { 0x5401b, 0x4866 },
        { 0x5401c, 0x4800 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x84 },
-       { 0x54020, 0x33 },
+       { 0x54020, 0xf3 },
        { 0x54021, 0x4866 },
        { 0x54022, 0x4800 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x3 },
        { 0x54032, 0x8400 },
-       { 0x54033, 0x3300 },
+       { 0x54033, 0xf300 },
        { 0x54034, 0x6600 },
        { 0x54035, 0x48 },
        { 0x54036, 0x48 },
        { 0x54037, 0x1600 },
        { 0x54038, 0x8400 },
-       { 0x54039, 0x3300 },
+       { 0x54039, 0xf300 },
        { 0x5403a, 0x6600 },
        { 0x5403b, 0x48 },
        { 0x5403c, 0x48 },
@@ -1146,25 +1161,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
        { 0x5400f, 0x100 },
        { 0x54012, 0x310 },
        { 0x54019, 0x84 },
-       { 0x5401a, 0x33 },
+       { 0x5401a, 0xf3 },
        { 0x5401b, 0x4866 },
        { 0x5401c, 0x4800 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x84 },
-       { 0x54020, 0x33 },
+       { 0x54020, 0xf3 },
        { 0x54021, 0x4866 },
        { 0x54022, 0x4800 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x3 },
        { 0x54032, 0x8400 },
-       { 0x54033, 0x3300 },
+       { 0x54033, 0xf300 },
        { 0x54034, 0x6600 },
        { 0x54035, 0x48 },
        { 0x54036, 0x48 },
        { 0x54037, 0x1600 },
        { 0x54038, 0x8400 },
-       { 0x54039, 0x3300 },
+       { 0x54039, 0xf300 },
        { 0x5403a, 0x6600 },
        { 0x5403b, 0x48 },
        { 0x5403c, 0x48 },
@@ -1175,7 +1190,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
 /* P0 2D message block paremeter for training firmware */
 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0xd0000, 0x0 },
-       { 0x54003, 0xe94 },
+       { 0x54003, 0xe10 },
        { 0x54004, 0x2 },
        { 0x54005, 0x2228 },
        { 0x54006, 0x14 },
@@ -1186,25 +1201,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54010, 0x1f7f },
        { 0x54012, 0x310 },
        { 0x54019, 0x36e4 },
-       { 0x5401a, 0x33 },
+       { 0x5401a, 0xf3 },
        { 0x5401b, 0x4866 },
        { 0x5401c, 0x4800 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x36e4 },
-       { 0x54020, 0x33 },
+       { 0x54020, 0xf3 },
        { 0x54021, 0x4866 },
        { 0x54022, 0x4800 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x3 },
        { 0x54032, 0xe400 },
-       { 0x54033, 0x3336 },
+       { 0x54033, 0xf336 },
        { 0x54034, 0x6600 },
        { 0x54035, 0x48 },
        { 0x54036, 0x48 },
        { 0x54037, 0x1600 },
        { 0x54038, 0xe400 },
-       { 0x54039, 0x3336 },
+       { 0x54039, 0xf336 },
        { 0x5403a, 0x6600 },
        { 0x5403b, 0x48 },
        { 0x5403c, 0x48 },
@@ -1694,9 +1709,9 @@ static struct dram_cfg_param ddr_phy_pie[] = {
        { 0x400d7, 0x20b },
        { 0x2003a, 0x2 },
        { 0x200be, 0x3 },
-       { 0x2000b, 0x419 },
-       { 0x2000c, 0xe9 },
-       { 0x2000d, 0x91c },
+       { 0x2000b, 0x3f4 },
+       { 0x2000c, 0xe1 },
+       { 0x2000d, 0x8ca },
        { 0x2000e, 0x2c },
        { 0x12000b, 0x70 },
        { 0x12000c, 0x19 },
@@ -1799,8 +1814,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
 
 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
        {
-               /* P0 3733mts 1D */
-               .drate = 3733,
+               /* P0 3600mts 1D */
+               .drate = 3600,
                .fw_type = FW_1D_IMAGE,
                .fsp_cfg = ddr_fsp0_cfg,
                .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1820,8 +1835,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
                .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
        },
        {
-               /* P0 3733mts 2D */
-               .drate = 3733,
+               /* P0 3600mts 2D */
+               .drate = 3600,
                .fw_type = FW_2D_IMAGE,
                .fsp_cfg = ddr_fsp0_2d_cfg,
                .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1840,5 +1855,19 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = {
        .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
        .ddrphy_pie = ddr_phy_pie,
        .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
-       .fsp_table = { 3733, 400, 100, },
+       .fsp_table = { 3600, 400, 100, },
 };
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void dh_imx8mp_dhcom_dram_scrub_32g_x32(void)
+{
+       ddrc_inline_ecc_scrub(0x0,0x7ffffff);
+       ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
+       ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
+       ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
+       ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
+       ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
+       ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
+       ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
+}
+#endif

diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c
index 21b12a70c8ea775541195168423ed1e667388425..7d228da8e5b73181adf28754e0cc2f0b6a14844a 100644 (file)
--- a/board/dhelectronics/dh_imx8mp/spl.c
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <asm-generic/gpio.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
 #include <asm/arch/imx8mp_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
@@ -134,7 +135,34 @@ static void spl_dram_init(void)
        }
 
        ddr_init(dram_timing_info[memcfg]);
+
+       printf("DDR:   Inline ECC %sabled\n",
+              (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
+              "en" : "dis");
+}
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+static const scrub_func_t dram_scrub_fn[8] = {
+       NULL,                                   /* 512 MiB */
+       NULL,                                   /* 1024 MiB */
+       NULL,                                   /* 1536 MiB */
+       dh_imx8mp_dhcom_dram_scrub_16g_x32,     /* 2048 MiB */
+       NULL,                                   /* 3072 MiB */
+       dh_imx8mp_dhcom_dram_scrub_32g_x32,     /* 4096 MiB */
+       NULL,                                   /* 6144 MiB */
+       NULL,                                   /* 8192 MiB */
+};
+
+void board_dram_ecc_scrub(void)
+{
+       u8 memcfg = dh_get_memcfg();
+
+       if (!dram_scrub_fn[memcfg])
+               return;
+
+       dram_scrub_fn[memcfg]();
 }
+#endif
 
 void spl_board_init(void)
 {

diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 09481343bc6ce429ca50b3dbc7ad8f14417299c6..e072d7adca07b981a88e824548d4fc104fcf2bce 100644 (file)
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -50,7 +50,7 @@ CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MAX_SIZE=0x26000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x96fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
@@ -161,6 +161,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MP=y
 CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
 CONFIG_DFU_TFTP=y
 CONFIG_DFU_TIMEOUT=y
 CONFIG_DFU_MMC=y

diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 86121c7d9a4b366f3ba4742ddb796fa05b665907..d0ace794bb261d84eeed5409ef0437a1703315ca 100644 (file)
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -51,7 +51,7 @@ CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MAX_SIZE=0x26000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x96fc00
 CONFIG_SPL_BSS_MAX_SIZE=0x400
@@ -163,6 +163,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MP=y
 CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
 CONFIG_DFU_TFTP=y
 CONFIG_DFU_TIMEOUT=y
 CONFIG_DFU_MMC=y