config KM_IVM_BUS
int "IVM I2C Bus"
default 0 if ARCH_SOCFPGA
- default 1 if MPC85xx || ARCH_LS1021A
- default 2 if MPC83xx
+ default 1 if PPC || ARCH_LS1021A
help
Identifier number of I2C bus, where the inventory EEPROM is connected to.
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o
+obj-y += km83xx.o ../common/common.o ../common/ivm.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <linux/ctype.h>
-#include <linux/delay.h>
-#include "../common/common.h"
-
-static void i2c_write_start_seq(void)
-{
- struct fsl_i2c_base *base;
- base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
- CONFIG_SYS_FSL_I2C_OFFSET);
- udelay(DELAY_ABORT_SEQ);
- out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- out_8(&base->cr, (I2C_CR_MEN));
-}
-
-int i2c_make_abort(void)
-{
- struct fsl_i2c_base *base;
- base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
- CONFIG_SYS_FSL_I2C_OFFSET);
- uchar last;
- int nbr_read = 0;
- int i = 0;
- int ret = 0;
-
- /* wait after each operation to finsh with a delay */
- out_8(&base->cr, (I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- in_8(&base->dr);
- udelay(DELAY_ABORT_SEQ);
- last = in_8(&base->dr);
- nbr_read++;
-
- /*
- * do read until the last bit is 1, but stop if the full eeprom is
- * read.
- */
- while (((last & 0x01) != 0x01) &&
- (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
- udelay(DELAY_ABORT_SEQ);
- last = in_8(&base->dr);
- nbr_read++;
- }
- if ((last & 0x01) != 0x01)
- ret = -2;
- if ((last != 0xff) || (nbr_read > 1))
- printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
- nbr_read, last);
- udelay(DELAY_ABORT_SEQ);
- out_8(&base->cr, (I2C_CR_MEN));
- udelay(DELAY_ABORT_SEQ);
- /* clear status reg */
- out_8(&base->sr, 0);
-
- for (i = 0; i < 5; i++)
- i2c_write_start_seq();
- if (ret != 0)
- printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
- nbr_read, last);
-
- return ret;
-}
CONFIG_SYS_BR4_PRELIM_BOOL=y
CONFIG_SYS_BR4_PRELIM=0xB0000801
CONFIG_SYS_OR4_PRELIM=0xF0000E25
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=200000
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xA0000801
CONFIG_SYS_OR3_PRELIM=0xF0000E25
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=200000
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0001001
CONFIG_SYS_OR3_PRELIM=0xF0000040
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=200000
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=200000
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0001001
CONFIG_SYS_OR3_PRELIM=0xF0000040
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=200000
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=200000
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0000801
CONFIG_SYS_OR3_PRELIM=0xF0000E24
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3000
-CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
-CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=200000
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
-/* I2C */
-#define CFG_SYS_NUM_I2C_BUSES 4
-#define CFG_SYS_I2C_MAX_HOPS 1
-#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
- {1, {I2C_NULL_HOP} } }
-
#if defined(CONFIG_CMD_NAND)
#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE
#endif