arm: ls102xa: clear EPU registers for deep sleep

After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index d82ce8d01430413b371ccd9f30636b5d96706142..ae4f25dcd3006ec2bb6e1e47b68a944c09c6ccbc 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -7,6 +7,7 @@
 obj-y  += cpu.o
 obj-y  += clock.o
 obj-y  += timer.o
+obj-y  += fsl_epu.o
 
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index b7dde45ed38436df934445c8e846b139e0f9fe59..fae6c68efc4744af38c8a49d2029a4b3dbef2fe7 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -12,6 +12,8 @@
 #include <netdev.h>
 #include <fsl_esdhc.h>
 
+#include "fsl_epu.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -101,3 +103,17 @@ int cpu_eth_init(bd_t *bis)
 
        return 0;
 }
+
+int arch_cpu_init(void)
+{
+       void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+
+       /*
+        * After wakeup from deep sleep, Clear EPU registers
+        * as early as possible to prevent from possible issue.
+        * It's also safe to clear at normal boot.
+        */
+       fsl_epu_clean(epu_base);
+
+       return 0;
+}

diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
new file mode 100644 (file)
index 0000000..6212640
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "fsl_epu.h"
+
+/**
+ * fsl_epu_clean - Clear EPU registers
+ */
+void fsl_epu_clean(void *epu_base)
+{
+       u32 offset;
+
+       /* follow the exact sequence to clear the registers */
+       /* Clear EPACRn */
+       for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPEVTCRn */
+       for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPGCR */
+       out_be32(epu_base + EPGCR, 0);
+
+       /* Clear EPSMCRn */
+       for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPCCRn */
+       for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPCMPRn */
+       for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPCTRn */
+       for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPIMCRn */
+       for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+               out_be32(epu_base + offset, 0);
+
+       /* Clear EPXTRIGCRn */
+       out_be32(epu_base + EPXTRIGCR, 0);
+
+       /* Clear EPECRn */
+       for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+               out_be32(epu_base + offset, 0);
+}

diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
new file mode 100644 (file)
index 0000000..d658aad
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_EPU_H
+#define __FSL_EPU_H
+
+#include <asm/types.h>
+
+#define FSL_STRIDE_4B  4
+#define FSL_STRIDE_8B  8
+
+/* Block offsets */
+#define EPU_BLOCK_OFFSET       0x00000000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR          0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0       0x050
+#define EPEVTCR9       0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR      0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0                0x100
+#define EPIMCR31       0x17C
+#define EPIMCR_STRIDE  FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0                0x200
+#define EPSMCR15       0x278
+#define EPSMCR_STRIDE  FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0         0x300
+#define EPECR15                0x33C
+#define EPECR_STRIDE   FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0         0x400
+#define EPACR15                0x43C
+#define EPACR_STRIDE   FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0         0x800
+#define EPCCR15                0x83C
+#define EPCCR31                0x87C
+#define EPCCR_STRIDE   FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0                0x900
+#define EPCMPR15       0x93C
+#define EPCMPR31       0x97C
+#define EPCMPR_STRIDE  FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0         0xA00
+#define EPCTR31                0xA7C
+#define EPCTR_STRIDE   FSL_STRIDE_4B
+
+void fsl_epu_clean(void *epu_base);
+
+#endif

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index ba86eea040295e1ad0240569c601951137e8059d..7d70c7bcbf342c49bbad6ab8de657ff275df3723 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -13,6 +13,7 @@
 #define OCRAM_SIZE                             0x00020000
 
 #define CONFIG_SYS_IMMR                                0x01000000
+#define CONFIG_SYS_DCSRBAR                     0x20000000
 
 #define CONFIG_SYS_FSL_DDR_ADDR                        (CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)