spi: zynqmp_gqspi: Fix write issue

Enable manual start in zynqmp_qspi_fill_gen_fifo().
Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of
GQSPI_IXR_GFEMTY_MASK.

Add dummy write to genfifo register in chipselect.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 17780066ae45498731b35348928e7ef9e5d9d22e..fc81b07343f964df777b31e74f9ab70770259d33 100644 (file)
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -39,6 +39,7 @@
 #define GQSPI_IXR_TXFULL_MASK          0x00000008 /* QSPI TX FIFO is full */
 #define GQSPI_IXR_RXNEMTY_MASK         0x00000010 /* QSPI RX FIFO Not Empty */
 #define GQSPI_IXR_GFEMTY_MASK          0x00000080 /* QSPI Generic FIFO Empty */
+#define GQSPI_IXR_GFNFULL_MASK         0x00000200 /* QSPI GENFIFO not full */
 #define GQSPI_IXR_ALL_MASK             (GQSPI_IXR_TXNFULL_MASK | \
                                         GQSPI_IXR_RXNEMTY_MASK)
 
@@ -238,9 +239,21 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
                                      u32 gqspi_fifo_reg)
 {
        struct zynqmp_qspi_regs *regs = priv->regs;
+       u32 config_reg, ier;
        int ret = 0;
 
-       ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
+       config_reg = readl(&regs->confr);
+       /* Manual start if needed */
+       config_reg |= GQSPI_STRT_GEN_FIFO;
+       writel(config_reg, &regs->confr);
+
+       /* Enable interrupts */
+       ier = readl(&regs->ier);
+       ier |= GQSPI_IXR_GFNFULL_MASK;
+       writel(ier, &regs->ier);
+
+       /* Wait until the fifo is not full to write the new command */
+       ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFNFULL_MASK, 1,
                                GQSPI_TIMEOUT, 1);
        if (ret)
                printf("%s Timeout\n", __func__);
@@ -263,6 +276,9 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 
        debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 
+       /* Dummy generic FIFO entry */
+       zynqmp_qspi_fill_gen_fifo(priv, 0);
+
        zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 }