]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm: meson: remove static ethernet link setup
authorNeil Armstrong <narmstrong@baylibre.com>
Thu, 25 Feb 2021 08:44:38 +0000 (09:44 +0100)
committerNeil Armstrong <narmstrong@baylibre.com>
Tue, 6 Apr 2021 09:10:29 +0000 (11:10 +0200)
The static ethernet link type config code is no more needed because now handled by
the meson8b glue driver, delete it.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
19 files changed:
arch/arm/include/asm/arch-meson/axg.h
arch/arm/include/asm/arch-meson/eth.h
arch/arm/include/asm/arch-meson/g12a.h
arch/arm/include/asm/arch-meson/gx.h
arch/arm/mach-meson/board-axg.c
arch/arm/mach-meson/board-g12a.c
arch/arm/mach-meson/board-gx.c
board/amlogic/beelink-s922x/beelink-s922x.c
board/amlogic/odroid-n2/odroid-n2.c
board/amlogic/p200/p200.c
board/amlogic/p201/p201.c
board/amlogic/p212/p212.c
board/amlogic/q200/q200.c
board/amlogic/s400/s400.c
board/amlogic/sei510/sei510.c
board/amlogic/sei610/sei610.c
board/amlogic/u200/u200.c
board/amlogic/vim3/vim3.c
board/amlogic/w400/w400.c

index 91c87696e0375087f3e7fa3aa9c24f63b297b2c6..12042de93590f6f7a1e87a7f9b8009babfc845e7 100644 (file)
 #define AXG_AO_BL31_RSVMEM_SIZE_SHIFT  16
 #define AXG_AO_BL32_RSVMEM_SIZE_MASK   0xFFFF
 
-/* Peripherals registers */
-#define AXG_PERIPHS_ADDR(off)  (AXG_PERIPHS_BASE + ((off) << 2))
-
-#define AXG_ETH_REG_0          AXG_PERIPHS_ADDR(0x50)
-#define AXG_ETH_REG_1          AXG_PERIPHS_ADDR(0x51)
-
-#define AXG_ETH_REG_0_PHY_INTF_RGMII   BIT(0)
-#define AXG_ETH_REG_0_PHY_INTF_RMII    BIT(2)
-#define AXG_ETH_REG_0_TX_PHASE(x)      (((x) & 3) << 5)
-#define AXG_ETH_REG_0_TX_RATIO(x)      (((x) & 7) << 7)
-#define AXG_ETH_REG_0_PHY_CLK_EN       BIT(10)
-#define AXG_ETH_REG_0_INVERT_RMII_CLK  BIT(11)
-#define AXG_ETH_REG_0_CLK_EN           BIT(12)
-
-/* HIU registers */
-#define AXG_HIU_ADDR(off)      (AXG_HIU_BASE + ((off) << 2))
-
-#define AXG_MEM_PD_REG_0       AXG_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define AXG_MEM_PD_REG_0_ETH_MASK      (BIT(2) | BIT(3))
-
 #endif /* __AXG_H__ */
index f765cd7c4ca1ba4c0bbc9bbb694017b229fab669..c0070615c2e54038242fcf6450e817e516796697 100644 (file)
@@ -7,18 +7,6 @@
 #ifndef __MESON_ETH_H__
 #define __MESON_ETH_H__
 
-#include <phy.h>
-
-enum {
-       /* Use Internal RMII PHY */
-       MESON_USE_INTERNAL_RMII_PHY = 1,
-};
-
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags);
-
 /* Generate an unique MAC address based on the HW serial */
 int meson_generate_serial_ethaddr(void);
 
index db29cc3a00f2244c0d5481042198ab784d548736..ef4f301f7d27de9652813d370a275d4116cde2e9 100644 (file)
 #define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
 #define G12A_AO_BL32_RSVMEM_SIZE_MASK  0xFFFF
 
-/* Peripherals registers */
-#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
-
-#define G12A_ETH_REG_0                 G12A_PERIPHS_ADDR(0x50)
-#define G12A_ETH_REG_1                 G12A_PERIPHS_ADDR(0x51)
-
-#define G12A_ETH_REG_0_PHY_INTF_RGMII  BIT(0)
-#define G12A_ETH_REG_0_PHY_INTF_RMII   BIT(2)
-#define G12A_ETH_REG_0_TX_PHASE(x)     (((x) & 3) << 5)
-#define G12A_ETH_REG_0_TX_RATIO(x)     (((x) & 7) << 7)
-#define G12A_ETH_REG_0_PHY_CLK_EN      BIT(10)
-#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
-#define G12A_ETH_REG_0_CLK_EN          BIT(12)
-
-#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
-#define ETH_PLL_CNTL0                  G12A_ETH_PHY_ADDR(0x11)
-#define ETH_PLL_CNTL1                  G12A_ETH_PHY_ADDR(0x12)
-#define ETH_PLL_CNTL2                  G12A_ETH_PHY_ADDR(0x13)
-#define ETH_PLL_CNTL3                  G12A_ETH_PHY_ADDR(0x14)
-#define ETH_PLL_CNTL4                  G12A_ETH_PHY_ADDR(0x15)
-#define ETH_PLL_CNTL5                  G12A_ETH_PHY_ADDR(0x16)
-#define ETH_PLL_CNTL6                  G12A_ETH_PHY_ADDR(0x17)
-#define ETH_PLL_CNTL7                  G12A_ETH_PHY_ADDR(0x18)
-#define ETH_PHY_CNTL0                  G12A_ETH_PHY_ADDR(0x20)
-#define ETH_PHY_CNTL1                  G12A_ETH_PHY_ADDR(0x21)
-#define ETH_PHY_CNTL2                  G12A_ETH_PHY_ADDR(0x22)
-
-/* HIU registers */
-#define G12A_HIU_ADDR(off)     (G12A_HIU_BASE + ((off) << 2))
-
-#define G12A_MEM_PD_REG_0              G12A_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define G12A_MEM_PD_REG_0_ETH_MASK     (BIT(2) | BIT(3))
-
 #endif /* __G12A_H__ */
index 743d2e8bb97b807ba7015d139e4bf202dfc80e57..26ec5d0bc340bc03587047d68a88042779e64536 100644 (file)
 #define GX_GPIO_IN(n)          GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
 #define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
 
-#define GX_ETH_REG_0           GX_PERIPHS_ADDR(0x50)
-#define GX_ETH_REG_1           GX_PERIPHS_ADDR(0x51)
-#define GX_ETH_REG_2           GX_PERIPHS_ADDR(0x56)
-#define GX_ETH_REG_3           GX_PERIPHS_ADDR(0x57)
-
-#define GX_ETH_REG_0_PHY_INTF          BIT(0)
-#define GX_ETH_REG_0_TX_PHASE(x)       (((x) & 3) << 5)
-#define GX_ETH_REG_0_TX_RATIO(x)       (((x) & 7) << 7)
-#define GX_ETH_REG_0_PHY_CLK_EN        BIT(10)
-#define GX_ETH_REG_0_INVERT_RMII_CLK   BIT(11)
-#define GX_ETH_REG_0_CLK_EN            BIT(12)
-
-/* HIU registers */
-#define GX_HIU_ADDR(off)       (GX_HIU_BASE + ((off) << 2))
-
-#define GX_MEM_PD_REG_0        GX_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define GX_MEM_PD_REG_0_ETH_MASK       (BIT(2) | BIT(3))
-
 #endif /* __GX_H__ */
index 3b14bc998944d99e292f3e1f950564bf624b8556..71ac65c636c87bded3f8dde022b4684b3adca7be 100644 (file)
@@ -91,40 +91,6 @@ static struct mm_region axg_mem_map[] = {
 
 struct mm_region *mem_map = axg_mem_map;
 
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags)
-{
-       switch (mode) {
-       case PHY_INTERFACE_MODE_RGMII:
-       case PHY_INTERFACE_MODE_RGMII_ID:
-       case PHY_INTERFACE_MODE_RGMII_RXID:
-       case PHY_INTERFACE_MODE_RGMII_TXID:
-               /* Set RGMII mode */
-               setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
-                            AXG_ETH_REG_0_TX_PHASE(1) |
-                            AXG_ETH_REG_0_TX_RATIO(4) |
-                            AXG_ETH_REG_0_PHY_CLK_EN |
-                            AXG_ETH_REG_0_CLK_EN);
-               break;
-
-       case PHY_INTERFACE_MODE_RMII:
-               /* Set RMII mode */
-               out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
-                                       AXG_ETH_REG_0_INVERT_RMII_CLK |
-                                       AXG_ETH_REG_0_CLK_EN);
-               break;
-
-       default:
-               printf("Invalid Ethernet interface mode\n");
-               return;
-       }
-
-       /* Enable power gate */
-       clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
-}
-
 #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
        CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
 static struct dwc2_plat_otg_data meson_gx_dwc2_data;
index cc7e01d014050dca4563b6fbc44ca443c8b50176..2e59eee8f7924ecb94320d7a89c2b80510295739 100644 (file)
@@ -97,37 +97,6 @@ static struct mm_region g12a_mem_map[] = {
 
 struct mm_region *mem_map = g12a_mem_map;
 
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags)
-{
-       switch (mode) {
-       case PHY_INTERFACE_MODE_RGMII:
-       case PHY_INTERFACE_MODE_RGMII_ID:
-       case PHY_INTERFACE_MODE_RGMII_RXID:
-       case PHY_INTERFACE_MODE_RGMII_TXID:
-               /* Set RGMII mode */
-               setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
-                            G12A_ETH_REG_0_TX_PHASE(1) |
-                            G12A_ETH_REG_0_TX_RATIO(4) |
-                            G12A_ETH_REG_0_PHY_CLK_EN |
-                            G12A_ETH_REG_0_CLK_EN);
-               break;
-
-       case PHY_INTERFACE_MODE_RMII:
-               /* Set RMII mode */
-               out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
-                                       G12A_ETH_REG_0_INVERT_RMII_CLK |
-                                       G12A_ETH_REG_0_CLK_EN);
-               break;
-
-       default:
-               printf("Invalid Ethernet interface mode\n");
-               return;
-       }
-}
-
 #if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
        CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
 static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
index cae7af5afb139d523d53345219c34fbe2f73aa61..01fafd81c48a8b20b9bf39ac2a4d7e8b16081e09 100644 (file)
@@ -109,41 +109,6 @@ static struct mm_region gx_mem_map[] = {
 
 struct mm_region *mem_map = gx_mem_map;
 
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_eth_init(phy_interface_t mode, unsigned int flags)
-{
-       switch (mode) {
-       case PHY_INTERFACE_MODE_RGMII:
-       case PHY_INTERFACE_MODE_RGMII_ID:
-       case PHY_INTERFACE_MODE_RGMII_RXID:
-       case PHY_INTERFACE_MODE_RGMII_TXID:
-               /* Set RGMII mode */
-               setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
-                            GX_ETH_REG_0_TX_PHASE(1) |
-                            GX_ETH_REG_0_TX_RATIO(4) |
-                            GX_ETH_REG_0_PHY_CLK_EN |
-                            GX_ETH_REG_0_CLK_EN);
-
-               break;
-
-       case PHY_INTERFACE_MODE_RMII:
-               /* Set RMII mode */
-               out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
-                                        GX_ETH_REG_0_CLK_EN);
-
-               if (!IS_ENABLED(CONFIG_MESON_GXBB))
-                       writel(0x10110181, GX_ETH_REG_2);
-
-               break;
-
-       default:
-               printf("Invalid Ethernet interface mode\n");
-               return;
-       }
-}
-
 #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
        CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
 static struct dwc2_plat_otg_data meson_gx_dwc2_data;
index dc0d933a39e6f6cd98d13dd2bd9828dfe2f1d8a8..bb7442626611aaa2cdb71a47a7ec6d4d63dbfc5d 100644 (file)
@@ -28,8 +28,6 @@ int misc_init_r(void)
            meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
                env_set("soc_rev", tmp);
 
-       meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
        if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
                len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
                                          efuse_mac_addr, EFUSE_MAC_SIZE);
index 863975e51b1a9eaac8b98b4deb175b3fd8b4710c..88a60f34fe8c70a8b78c1e54eaa92a66a0dcc8df 100644 (file)
@@ -115,8 +115,6 @@ int misc_init_r(void)
            meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
                env_set("soc_rev", tmp);
 
-       meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
        if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
                len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
                                          efuse_mac_addr, EFUSE_MAC_SIZE);
index 8f1bf8bfda47509878a026f92c3ea25387ed0b92..7c432f9d2810cfc64a4184d571b3a2b165a73960 100644 (file)
@@ -25,8 +25,6 @@ int misc_init_r(void)
        char serial[EFUSE_SN_SIZE];
        ssize_t len;
 
-       meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
        if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
                len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
                                          mac_addr, EFUSE_MAC_SIZE);
index 597bb71cbf7f4dd9c9d95f692e5b33a61a891f69..7c432f9d2810cfc64a4184d571b3a2b165a73960 100644 (file)
@@ -25,8 +25,6 @@ int misc_init_r(void)
        char serial[EFUSE_SN_SIZE];
        ssize_t len;
 
-       meson_eth_init(PHY_INTERFACE_MODE_RMII, 0);
-
        if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
                len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
                                          mac_addr, EFUSE_MAC_SIZE);
index fbc49e95651f20c99027d7c8e5b1a91d564ed94a..fcef90bce56f09113907558c55b0b45696f95da0 100644 (file)
@@ -26,9 +26,6 @@ int misc_init_r(void)
        char serial[EFUSE_SN_SIZE];
        ssize_t len;
 
-       meson_eth_init(PHY_INTERFACE_MODE_RMII,
-                      MESON_USE_INTERNAL_RMII_PHY);
-
        if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
                len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
                                          mac_addr, EFUSE_MAC_SIZE);
index 62e6fa3d199261bff7d3e82b1d96a2e6d849d9e7..3aa6d8f200e288fa19a275dd6b622f9c2eb08608 100644 (file)
@@ -26,8 +26,6 @@ int misc_init_r(void)
        char serial[EFUSE_SN_SIZE];
        ssize_t len;
 
-       meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
        if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
                len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
                                          mac_addr, EFUSE_MAC_SIZE);
index b081942dccfb8753b6f424ac509542f6a0c779f2..06a9044fd8087cc585a0ff356b63d933e65eb277 100644 (file)
@@ -16,8 +16,6 @@
 
 int misc_init_r(void)
 {
-       meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
        meson_generate_serial_ethaddr();
 
        return 0;
index 5a5148ea68eef12e3f8ef501622359df93b1e221..bb188c21f75f334730ee67b9c2bd7324be4cecd6 100644 (file)
@@ -18,9 +18,6 @@
 
 int misc_init_r(void)
 {
-       meson_eth_init(PHY_INTERFACE_MODE_RMII,
-                      MESON_USE_INTERNAL_RMII_PHY);
-
        meson_generate_serial_ethaddr();
 
        env_set("serial#", "AMLG12ASEI510");
index 27dba93582496502aa09f4a46eb60791df6d604f..6490bac9eb5576669e548d7f5e88a378ea8a81c9 100644 (file)
@@ -18,9 +18,6 @@
 
 int misc_init_r(void)
 {
-       meson_eth_init(PHY_INTERFACE_MODE_RMII,
-                      MESON_USE_INTERNAL_RMII_PHY);
-
        meson_generate_serial_ethaddr();
 
        env_set("serial#", "AMLG12ASEI610");
index 373235d77a974ad7568566bf239f2784434f864c..06a9044fd8087cc585a0ff356b63d933e65eb277 100644 (file)
@@ -16,8 +16,7 @@
 
 int misc_init_r(void)
 {
-       meson_eth_init(PHY_INTERFACE_MODE_RMII,
-                      MESON_USE_INTERNAL_RMII_PHY);
+       meson_generate_serial_ethaddr();
 
        return 0;
 }
index 7b09617cdc6b74e4f75c8c75301702ce7afe08d8..6cd5f2e115fe7ab6c53bd726281aaeb43600c415 100644 (file)
@@ -149,8 +149,6 @@ int misc_init_r(void)
        char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
        ssize_t len;
 
-       meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
        if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
                len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
                                          efuse_mac_addr, EFUSE_MAC_SIZE);
index 47a51710dc9b5e52c8e20656e5231f4ea3d2166d..4199198496b1817eecf547716f5431249216d441 100644 (file)
@@ -14,7 +14,7 @@
 
 int misc_init_r(void)
 {
-       meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+       meson_generate_serial_ethaddr();
 
        return 0;
 }