*/
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
#include <vsprintf.h>
{
timer_init();
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+ gd->cpu_clk = get_board_sys_clk();
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
cache_init();
*/
#include <common.h>
+#include <clock_legacy.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <div64.h>
/*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
/*
* return the PLL output frequency
*
- * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
* / (X2IPD + 1) / 2^PS
*/
static ulong get_PLLCLK(uint32_t *pllreg)
{
uint8_t i;
const uint32_t clkset = readl(pllreg);
- uint64_t rate = CONFIG_SYS_CLK_FREQ;
+ uint64_t rate = get_board_sys_clk();
rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
const uint32_t value = readl(&syscon->pwrcnt);
if (value & SYSCON_PWRCNT_UART_BAUD)
- uclk_rate = CONFIG_SYS_CLK_FREQ;
+ uclk_rate = get_board_sys_clk();
else
- uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+ uclk_rate = get_board_sys_clk() / 2;
return uclk_rate;
}
#include <common.h>
#if defined (CONFIG_IMX)
+#include <clock_legacy.h>
#include <asm/arch/imx-regs.h>
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
* SH FIXME: 16780000 in our case
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
mfi = mfi<=5 ? 5 : mfi;
- return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+ return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_FCLK(void)
uint i;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
sys_info->freq_systembus = sysclk;
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
sysclk_path = fdt_get_alias(blob, "sysclk");
if (sysclk_path)
do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
- CONFIG_SYS_CLK_FREQ, 1);
+ get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
#define UBOOT_HEAD_LEN 0x1000
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <fsl_ddr_sdram.h>
* controller is used, SYSCLK must meet the additional requirement
* of 100 MHz.
*/
- if (CONFIG_SYS_CLK_FREQ != 100000000) {
+ if (get_board_sys_clk() != 100000000) {
off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
while (off != -FDT_ERR_NOTFOUND) {
fdt_status_disabled(blob, off);
#endif
do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
- CONFIG_SYS_CLK_FREQ, 1);
+ get_board_sys_clk(), 1);
#ifdef CONFIG_GIC_V3_ITS
ls_gic_rd_tables_init(blob);
uint i, cluster;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
unsigned long cluster_clk;
sys_info->freq_systembus = sysclk;
#ifndef CONFIG_CLUSTER_CLK_FREQ
-#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_CLUSTER_CLK_FREQ get_board_sys_clk()
#endif
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
#endif
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
u32 c_pll_sel, cplx_pll;
void *offset;
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <image.h>
#include <log.h>
*/
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <asm/arch/hardware.h>
#include <asm/global_data.h>
*/
#include <common.h>
+#include <clock_legacy.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
/* SDIV [2:0] */
s = r & 0x7;
- freq = CONFIG_SYS_CLK_FREQ;
+ freq = get_board_sys_clk();
if (pllreg == EPLL || pllreg == RPLL) {
k = k & 0xffff;
RPLL};
sclk = get_pll_clk(reg_map[sel]);
} else
- sclk = CONFIG_SYS_CLK_FREQ;
+ sclk = get_board_sys_clk();
/*
* CLK_DIV_DISP10
* FIMD1_RATIO [3:0]
*/
#ifndef CONFIG_TIMER
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <irq_func.h>
#include <log.h>
lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
#else
lastdec = readl(&tmr->timer3_counter) /
- (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
+ (get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
#endif
timestamp = 0; /* start "advancing" time stamp from 0 */
ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
#else
ulong now = readl(&tmr->timer3_counter) /
- (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ);
+ (get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
#endif
debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
#ifdef CONFIG_FTTMR010_EXT_CLK
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
#else
- long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+ long tmo = usec * ((get_board_sys_clk() / 2) / 1000) / 1000;
#endif
unsigned long now, last = readl(&tmr->timer3_counter);
#ifdef CONFIG_FTTMR010_EXT_CLK
return CONFIG_SYS_HZ;
#else
- return CONFIG_SYS_CLK_FREQ;
+ return get_board_sys_clk();
#endif
}
#endif /* CONFIG_TIMER */
*/
#include <common.h>
+#include <clock_legacy.h>
#include <pci.h>
#include <mpc83xx.h>
#include <asm/global_data.h>
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
sccr = im->clk.sccr;
- pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+ pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_SYS_CLK_FREQ)
- pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+#if CONFIG_SYS_CLK_FREQ != 0
+ pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
- return CONFIG_SYS_CLK_FREQ * spmf;
+ return get_board_sys_clk() * spmf;
}
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0)/2, 1);
#else
uint rcw_tmp;
#endif
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
uint mem_pll_rat;
sys_info->freq_systembus = sysclk;
* are driven by differential sysclock.
*/
if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
- sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_ddrbus = get_board_sys_clk();
else
#endif
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
- sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
- sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_qe = qe_ratio * get_board_sys_clk();
#endif
#endif
/* Timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
+#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
#endif
*/
#include <common.h>
+#include <clock_legacy.h>
#include <time.h>
#include <asm/global_data.h>
#include <linux/delay.h>
void __udelay(unsigned long usec)
{
ulong lo, hi, i;
- ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000;
+ ulong mhz = get_board_sys_clk() / 1000000;
/* Scale to support full 32-bit usec range */
#if XCHAL_HAVE_CCOUNT
register ulong ccount;
__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
- return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
+ return ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
#else
/*
* Add at least the overhead of this call (in cycles).
*/
fake_ccount += 20;
- return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base;
+ return fake_ccount / (get_board_sys_clk() / CONFIG_SYS_HZ) - base;
#endif
}
unsigned long ccount;
__asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount));
- return ccount / (CONFIG_SYS_CLK_FREQ / 1000000);
+ return ccount / (get_board_sys_clk() / 1000000);
}
#endif
*/
#include <common.h>
+#include <clock_legacy.h>
#include <command.h>
#include <dm.h>
#include <init.h>
#include <common.h>
-
+#include <clock_legacy.h>
/*
* CADMUS Board System Registers
*/
#include <common.h>
+#include <clock_legacy.h>
#include <log.h>
#include <asm/io.h>
*/
#include <common.h>
+#include <clock_legacy.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>
*/
#include <common.h>
+#include <clock_legacy.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_ddr_sdram.h>
* Copyright 2017-2018 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
* Copyright 2015 Freescale Semiconductor
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
* Copyright 2017 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <mpc85xx.h>
#include <asm/io.h>
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ bus_clk = get_board_sys_clk() * plat_ratio;
gd->bus_clk = bus_clk;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
*/
#include <common.h>
+#include <clock_legacy.h>
#include <init.h>
#include <ns16550.h>
#include <asm/io.h>
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = get_board_sys_clk() * plat_ratio;
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
*/
#include <common.h>
+#include <clock_legacy.h>
#include <command.h>
#include <env.h>
#include <fdt_support.h>
#endif
/* initialize selected port with appropriate baud rate */
- sys_clk = CONFIG_SYS_CLK_FREQ;
+ sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = CONFIG_SYS_CLK_FREQ;
+ sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
uart_clk = sys_clk * plat_ratio / 2;
*/
#include <common.h>
+#include <clock_legacy.h>
#include <command.h>
#include <env.h>
#include <fdt_support.h>
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = CONFIG_SYS_CLK_FREQ;
+ sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = CONFIG_SYS_CLK_FREQ;
+ sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 0.8GHz */
- stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
+ stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
- stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
- stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <env_internal.h>
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
u32 stat = 0;
- u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+ u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
*/
#include <common.h>
+#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
- stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */
*/
#include <common.h>
+#include <clock_legacy.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
u32 stat = 0;
- u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+ u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* Check the PCI_clk sel bit */
if (in_be32(&gur->porpllsr) & (1<<15)) {
src = "SYSCLK";
- f = CONFIG_SYS_CLK_FREQ;
+ f = get_board_sys_clk();
} else {
src = "PCI_CLK";
f = CONFIG_PCI_CLK_FREQ;
*/
#include <common.h>
+#include <clock_legacy.h>
#include <dm.h>
#include <env.h>
#include <hang.h>
* assured it's being powered with suitable core voltage
*/
if (!power_failed)
- clock_set_pll1(CONFIG_SYS_CLK_FREQ);
+ clock_set_pll1(get_board_sys_clk());
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
}
*/
#include <common.h>
+#include <clock_legacy.h>
#include <asm/io.h>
/*
help
The address in memory that U-Boot will be running from, initially.
+config DYNAMIC_SYS_CLK_FREQ
+ bool "Determine CPU clock frequency at run-time"
+ help
+ Implement a get_board_sys_clk function that will determine the CPU
+ clock frequency at run time, rather than define it statically.
+
config SYS_CLK_FREQ
- depends on ARC || ARCH_SUNXI || MPC83xx
+ depends on !DYNAMIC_SYS_CLK_FREQ
int "CPU clock frequency"
+ default 125000000 if ARCH_LS1012A
+ default 100000000 if ARCH_P2020 || ARCH_T1024 || ARCH_T1042 || \
+ ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+ default 66666666 if ARCH_P1010 || ARCH_P1020 || ARCH_T4240
+ default 66660000 if ARCH_T2080
+ default 33333333 if RCAR_GEN3
+ default 24000000 if ARCH_EXYNOS
+ default 20000000 if RCAR_GEN2
+ default 0
help
- TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
+ A static value for the CPU frequency. Note that if not required
+ for a given SoC, this can be left at 0.
config ARCH_FIXUP_FDT_MEMORY
bool "Enable arch_fixup_memory_banks() call"
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p2041rdb.cfg"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p3041ds.cfg"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p4080ds.cfg"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/corenet_ds/pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/corenet_ds/rcw_p5040ds.cfg"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ENV_OFFSET=0x140000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
+CONFIG_SYS_CLK_FREQ=39062500
CONFIG_TARGET_ADP_AE3XX=y
CONFIG_SYS_LOAD_ADDR=0x300000
CONFIG_FIT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="ag101p"
+CONFIG_SYS_CLK_FREQ=39062500
CONFIG_TARGET_ADP_AG101P=y
CONFIG_SYS_LOAD_ADDR=0x300000
CONFIG_FIT=y
CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board"
CONFIG_R8A7740=y
CONFIG_TARGET_ARMADILLO_800EVA=y
+CONFIG_SYS_CLK_FREQ=50000000
CONFIG_SYS_LOAD_ADDR=0x44000000
CONFIG_BOOTDELAY=3
# CONFIG_CMDLINE_EDITING is not set
CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
CONFIG_LTO=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
CONFIG_RZA1=y
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_SYS_LOAD_ADDR=0x20400000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC85xx=y
CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3"
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_BOOT"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1043aqds/ls1043aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1046aqds/ls1046aqds_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x806c0000 0x6c0000 0x40000; env exists mcinitcmd && env exists secureboot && esbc_validate 0x806C0000; sf read 0x80d00000 0xd00000 0x100000; env exists mcinitcmd && fsl_mc lazyapply dpl 0x80d00000; run distro_bootcmd;run qspi_bootcmd; env exists secureboot && esbc_halt;"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS1,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0600 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_MISC_INIT_R=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0xc0700000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run envboot; run mmcboot; "
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_SYS_TEXT_BASE=0xf01000
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500"
+CONFIG_SYS_CLK_FREQ=33000000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_QEMU_PPCE500=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus"
+CONFIG_SYS_CLK_FREQ=60000000
CONFIG_TARGET_R2DPLUS=y
CONFIG_SYS_LOAD_ADDR=0x8e000000
CONFIG_BOOTDELAY=-1
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_FALCON=y
+CONFIG_SYS_CLK_FREQ=16666666
# CONFIG_PSCI_RESET is not set
CONFIG_ARMV8_PSCI=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
CONFIG_TARGET_SMDKC100=y
CONFIG_IDENT_STRING=" for SMDKC100"
+CONFIG_SYS_CLK_FREQ=12000000
CONFIG_SYS_LOAD_ADDR=0x30000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x1E0000
+CONFIG_SYS_CLK_FREQ=27000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_XTFPGA_KC705=y
CONFIG_SYS_LOAD_ADDR=0x02000000
+CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_BOOTDELAY=10
CONFIG_AUTOBOOT_KEYED=y
u8 clkin_div;
clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT;
- return CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+ return get_board_sys_clk() / (1 + clkin_div);
}
/**
u8 spmf;
spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
- return CONFIG_SYS_CLK_FREQ * spmf;
+ return get_board_sys_clk() * spmf;
}
/**
*/
#include <common.h>
+#include <clock_legacy.h>
#include <clk.h>
#include <dm.h>
#include <fsl_lpuart.h>
}
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 0
-#endif
-
u32 __weak get_lpuart_clk(void)
{
- return CONFIG_SYS_CLK_FREQ;
+ return get_board_sys_clk();
}
#if CONFIG_IS_ENABLED(CLK)
*/
#include <common.h>
+#include <clock_legacy.h>
#include <malloc.h>
#include <asm/global_data.h>
#include <asm/io.h>
clk_free(&clk);
#else
- uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2;
+ uc_priv->clock_rate = get_board_sys_clk() / 2;
#endif
readb(priv->regs + OSTM_CTL);
#define get_board_ddr_clk() CONFIG_DDR_CLK_FREQ
#endif
+/*
+ * If we have CONFIG_DYNAMIC_SYS_CLK_FREQ then there will be an
+ * implentation of get_board_sys_clk() somewhere. Otherwise we have
+ * a static value to use now.
+ */
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
+unsigned long get_board_sys_clk(void);
+#else
+#define get_board_sys_clk() CONFIG_SYS_CLK_FREQ
+#endif
+
#endif
* Note that PCI-X won't work at 33MHz.
*/
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33000000
-#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(void);
#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
/*
* These can be toggled for performance analysis, otherwise use default.
* in the README.mpc85xxads.
*/
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33000000
-#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
-#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
-
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
#endif
#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
#include <linux/stringify.h>
#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
-#define CONFIG_SYS_CLK_FREQ 100000000
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#endif
#endif
-#define CONFIG_SYS_CLK_FREQ 100000000
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_CLK_FREQ 66660000
-
/*
* Config the L3 Cache as L3 SRAM
*/
"setenv bootargs config-addr=0x60000000; " \
"bootm 0x01000000 - 0x00f00000"
-#define CONFIG_SYS_CLK_FREQ 66666666
-
/*
* DDR Setup
*/
/*
* Timer
*/
-#define CONFIG_SYS_CLK_FREQ 39062500
-#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+#define VERSION_CLOCK get_board_sys_clk()
/*
* Use Externel CLOCK or PCLK
/*
* Timer
*/
-#define CONFIG_SYS_CLK_FREQ 39062500
-#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+#define VERSION_CLOCK get_board_sys_clk()
/*
* Use Externel CLOCK or PCLK
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
+#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ get_board_sys_clk()
#endif /* __ARMADILLO_800EVA_H */
#endif
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 20000000
/* ENV setting */
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-#define CONFIG_SYS_CLK_FREQ 33333333
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
#define CONFIG_FSL_FIXED_MMC_LOCATION
#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
/*
* SoC Configuration
*/
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-#define CONFIG_SYS_CLK_FREQ 33333333
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 24000000
-#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ
+#define COUNTER_FREQUENCY 24000000
/* select serial console configuration */
/* Board Clock */
/* XTAL_CLK : 16.66MHz */
-#define CONFIG_SYS_CLK_FREQ 16666666
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define __GRPEACH_H
/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
-#define CONFIG_SYS_CLK_FREQ 66666666
/* Miscellaneous */
#define CONFIG_SYS_PBSIZE 256
/*
* System Clock Setup
*/
-#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/* QE microcode/firmware address */
/*
* System Clock Setup
*/
-#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
CONFIG_KM_PHRAM + \
CONFIG_KM_RESERVED_PRAM) >> 10)
-#define CONFIG_SYS_CLK_FREQ 66666666
-
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_ENV_TOTAL_SIZE 0x040000
#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/
-#define CONFIG_SYS_CLK_FREQ 66666666
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
/*
* System Clock Setup
*/
-#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/**
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
/* serial port */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
/* ethernet */
#define CONFIG_SYS_RX_ETH_BUFFER 8
/* Clock */
#define CONFIG_GLOBAL_TIMER
-#define CONFIG_SYS_CLK_FREQ (48000000)
#define CONFIG_SYS_CPU_CLK (1196000000)
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ get_board_sys_clk()
#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
#define CONFIG_NFS_TIMEOUT 10000UL
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
/*
* SoC Configuration
*/
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#include <asm/arch/stream_id_lsch2.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_CLK_FREQ 125000000
-
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#else
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#define CONFIG_SYS_CLK_FREQ 100000000
-
/*
* DDR: 800 MHz ( 1600 MT/s data rate )
*/
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_QIXIS_I2C_ACCESS
-#else
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#endif
#ifdef CONFIG_SD_BOOT
/* XHCI Support - enabled by default */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define DDR_CS0_CONFIG 0x80014302
#include "ls1028a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#include "ls1028a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
#define CONFIG_SYS_RTC_BUS_NUM 0
#include "ls1043a_common.h"
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#include "ls1043a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#include "ls1046a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#include "ls1046a_common.h"
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#include "ls1046a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#include "ls1088a_common.h"
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
#define SYS_NO_FLASH
-
-#define CONFIG_SYS_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#endif
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define SYS_NO_FLASH
#endif
-#define CONFIG_SYS_CLK_FREQ 100000000
#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#include "ls2080a_common.h"
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
#endif
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#endif
#endif
-/* GPIO */
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
/*
* SoC Configuration
*/
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48
-#if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_SYS_CLK_FREQ 100000000
-#else
-#define CONFIG_SYS_CLK_FREQ 66666666
-#endif
-
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define CONFIG_CHIP_SELECTS_PER_CTRL 0
-#define CONFIG_SYS_CLK_FREQ 33000000
-
#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/*
* SuperH Clock setting
*/
-#define CONFIG_SYS_CLK_FREQ 60000000
#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
/*
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8)
+#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
#endif /* __RCAR_GEN2_COMMON_H */
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#include <asm/arch/cpu.h> /* get chip and board defs */
/* input clock of PLL: SMDKC100 has 12MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 12000000
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
* in the README.mpc85xxads.
*/
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66666666
-#endif
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
/**
* Platform/Board specific defs
*/
-#define CONFIG_SYS_CLK_FREQ 27000000
#define CONFIG_SYS_TIMERBASE 0x4802E000
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_XTFPGA
-/* FPGA CPU freq after init */
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-
/*===================*/
/* RAM Layout */
/*===================*/
#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_NS16550_CLK get_board_sys_clk()
/*======================*/
/* Ethernet Driver Info */
#ifndef __FTWDT010_H
#define __FTWDT010_H
+#include <clock_legacy.h>
+
struct ftwdt010_wdt {
unsigned int wdcounter; /* Counter Reg - 0x00 */
unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */
/*
* Variable timeout should be set in ms.
- * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms.
+ * (get_board_sys_clk()/1000) equals 1 ms.
* WDLOAD = timeout * TIMEOUT_FACTOR.
*/
-#define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */
+#define FTWDT010_TIMEOUT_FACTOR (get_board_sys_clk() / 1000) /* 1 ms */
void ftwdt010_wdt_reset(void);
void ftwdt010_wdt_disable(void);
*/
#include <common.h>
+#include <clock_legacy.h>
#include <bootstage.h>
#include <dm.h>
#include <errno.h>
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