COBJS += gpio.o
endif
-ifdef CONFIG_OMAP44XX
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
COBJS += hwinit-common.o
COBJS += clocks-common.o
COBJS += emif-common.o
endif
ifndef CONFIG_SPL_BUILD
-ifdef CONFIG_OMAP44XX
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
COBJS += mem-common.o
endif
endif
#define puts(s)
#endif
-#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
-
-struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
-
-static const u32 sys_clk_array[8] = {
- 12000000, /* 12 MHz */
- 13000000, /* 13 MHz */
- 16800000, /* 16.8 MHz */
- 19200000, /* 19.2 MHz */
- 26000000, /* 26 MHz */
- 27000000, /* 27 MHz */
- 38400000, /* 38.4 MHz */
-};
-
-/*
- * The M & N values in the following tables are created using the
- * following tool:
- * tools/omap/clocks_get_m_n.c
- * Please use this tool for creating the table for any new frequency.
- */
-
-/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
-static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
- {230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
-static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
- {66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
-static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
- {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
- {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
- {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
- {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
- {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
- {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
- {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
- {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
- {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
- {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
- {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
- {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
- {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
- {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
- {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
- {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
- {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
- {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
- {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
- {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
- {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
- {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
- {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
- {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
- {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
- {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
- {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
- {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
- {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
- {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1
-};
-
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
- {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
- {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
- {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
static inline u32 __get_sys_clk_index(void)
{
u32 ind;
if (lock)
do_lock_dpll(base);
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, &dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, &dpll_regs->cm_div_m3_dpll);
- if (params->m4 >= 0)
- writel(params->m4, &dpll_regs->cm_div_m4_dpll);
- if (params->m5 >= 0)
- writel(params->m5, &dpll_regs->cm_div_m5_dpll);
- if (params->m6 >= 0)
- writel(params->m6, &dpll_regs->cm_div_m6_dpll);
- if (params->m7 >= 0)
- writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+ setup_post_dividers(base, params);
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);
}
-const struct dpll_params *get_core_dpll_params(void)
+u32 omap_ddr_clk(void)
{
- u32 sysclk_ind = get_sys_clk_index();
-
- switch (omap_revision()) {
- case OMAP4430_ES1_0:
- return &core_dpll_params_es1_1524mhz[sysclk_ind];
- case OMAP4430_ES2_0:
- case OMAP4430_SILICON_ID_INVALID:
- /* safest */
- return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
- default:
- return &core_dpll_params_1600mhz[sysclk_ind];
- }
-}
-
-u32 omap4_ddr_clk(void)
-{
- u32 ddr_clk, sys_clk_khz;
+ u32 ddr_clk, sys_clk_khz, omap_rev, divider;
const struct dpll_params *core_dpll_params;
+ omap_rev = omap_revision();
sys_clk_khz = get_sys_clk_freq() / 1000;
core_dpll_params = get_core_dpll_params();
/* Find Core DPLL locked frequency first */
ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
(core_dpll_params->n + 1);
- /*
- * DDR frequency is PHY_ROOT_CLK/2
- * PHY_ROOT_CLK = Fdpll/2/M2
- */
- ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
+ if (omap_rev < OMAP5430_ES1_0) {
+ /*
+ * DDR frequency is PHY_ROOT_CLK/2
+ * PHY_ROOT_CLK = Fdpll/2/M2
+ */
+ divider = 4;
+ } else {
+ /*
+ * DDR frequency is PHY_ROOT_CLK
+ * PHY_ROOT_CLK = Fdpll/2/M2
+ */
+ divider = 2;
+ }
+
+ ddr_clk = ddr_clk / divider / core_dpll_params->m2;
ddr_clk *= 1000; /* convert to Hz */
debug("ddr_clk %d\n ", ddr_clk);
{
const struct dpll_params *params;
struct dpll_regs *mpu_dpll_regs;
- u32 omap4_rev, sysclk_ind;
-
- omap4_rev = omap_revision();
- sysclk_ind = get_sys_clk_index();
-
- if (omap4_rev == OMAP4430_ES1_0)
- params = &mpu_dpll_params_1200mhz[sysclk_ind];
- else if (omap4_rev < OMAP4460_ES1_0)
- params = &mpu_dpll_params_1584mhz[sysclk_ind];
- else
- params = &mpu_dpll_params_1840mhz[sysclk_ind];
+ u32 omap_rev;
+ omap_rev = omap_revision();
- /* DCC and clock divider settings for 4460 */
- if (omap4_rev >= OMAP4460_ES1_0) {
+ /*
+ * DCC and clock divider settings for 4460.
+ * DCC is required, if more than a certain frequency is required.
+ * For, 4460 > 1GHZ.
+ * 5430 > 1.4GHZ.
+ */
+ if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
mpu_dpll_regs =
(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
CM_CLKSEL_DCC_EN_MASK);
}
+ params = get_mpu_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
debug("MPU DPLL locked\n");
}
debug("Core DPLL configured\n");
/* lock PER dpll */
+ params = get_per_dpll_params();
do_setup_dpll(&prcm->cm_clkmode_dpll_per,
- &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
+ params, DPLL_LOCK);
debug("PER DPLL locked\n");
/* MPU dpll */
clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
- do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
- &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
+ params = get_iva_dpll_params();
+ do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK);
/*
* USB:
* Use CLKINP in KHz and adjust the denominator accordingly so
* that we have enough accuracy and at the same time no overflow
*/
- params = &usb_dpll_params_1920mhz[sysclk_ind];
+ params = get_usb_dpll_params();
num = params->m * sys_clk_khz;
den = (params->n + 1) * 250 * 1000;
num += den - 1;
/* Now setup the dpll with the regular function */
do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
-#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
- params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+ /* Configure ABE dpll */
+ params = get_abe_dpll_params();
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
#else
- params = &abe_dpll_params_32k_196608khz;
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
/*
* We need to enable some additional options to achieve
do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
}
-static void do_scale_tps62361(u32 reg, u32 volt_mv)
+void do_scale_tps62361(u32 reg, u32 volt_mv)
{
u32 temp, step;
}
}
-static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
{
u32 temp, offset_code;
u32 step = 12660; /* 12.66 mV represented in uV */
}
}
-/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
- */
-static void scale_vcores(void)
-{
- u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
-
- sys_clk_khz = get_sys_clk_freq() / 1000;
-
- /*
- * Setup the dedicated I2C controller for Voltage Control
- * I2C clk - high period 40% low period 60%
- */
- cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
- cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
- /* values to be set in register - less by 5 & 7 respectively */
- cycles_hi -= 5;
- cycles_low -= 7;
- temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
- (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
- writel(temp, &prcm->prm_vc_cfg_i2c_clk);
-
- /* Disable high speed mode and all advanced features */
- writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
-
- omap4_rev = omap_revision();
- /* TPS - supplies vdd_mpu on 4460 */
- if (omap4_rev >= OMAP4460_ES1_0) {
- volt = 1430;
- do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
- }
-
- /*
- * VCORE 1
- *
- * 4430 : supplies vdd_mpu
- * Setting a high voltage for Nitro mode as smart reflex is not enabled.
- * We use the maximum possible value in the AVS range because the next
- * higher voltage in the discrete range (code >= 0b111010) is way too
- * high
- *
- * 4460 : supplies vdd_core
- */
- if (omap4_rev < OMAP4460_ES1_0) {
- volt = 1417;
- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
- } else {
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
- }
-
- /* VCORE 2 - supplies vdd_iva */
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
-
- /*
- * VCORE 3
- * 4430 : supplies vdd_core
- * 4460 : not connected
- */
- if (omap4_rev < OMAP4460_ES1_0) {
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
- }
-}
-
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
wait_for_clk_enable(clkctrl_addr);
}
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-static void enable_basic_clocks(void)
-{
- u32 i, max = 100, wait_for_enable = 1;
- u32 *const clk_domains_essential[] = {
- &prcm->cm_l4per_clkstctrl,
- &prcm->cm_l3init_clkstctrl,
- &prcm->cm_memif_clkstctrl,
- &prcm->cm_l4cfg_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- &prcm->cm_wkup_gpio1_clkctrl,
- &prcm->cm_l4per_gpio2_clkctrl,
- &prcm->cm_l4per_gpio3_clkctrl,
- &prcm->cm_l4per_gpio4_clkctrl,
- &prcm->cm_l4per_gpio5_clkctrl,
- &prcm->cm_l4per_gpio6_clkctrl,
- &prcm->cm_memif_emif_1_clkctrl,
- &prcm->cm_memif_emif_2_clkctrl,
- &prcm->cm_l3init_hsusbotg_clkctrl,
- &prcm->cm_l3init_usbphy_clkctrl,
- &prcm->cm_l4cfg_l4_cfg_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_l4per_gptimer2_clkctrl,
- &prcm->cm_l3init_hsmmc1_clkctrl,
- &prcm->cm_l3init_hsmmc2_clkctrl,
- &prcm->cm_l4per_mcspi1_clkctrl,
- &prcm->cm_wkup_gptimer1_clkctrl,
- &prcm->cm_l4per_i2c1_clkctrl,
- &prcm->cm_l4per_i2c2_clkctrl,
- &prcm->cm_l4per_i2c3_clkctrl,
- &prcm->cm_l4per_i2c4_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_l4per_uart3_clkctrl,
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- /* Enable optional 48M functional clock for USB PHY */
- setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
- USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
-
- /* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
- enable_clock_domain(clk_domains_essential[i],
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- }
-
- /* Clock modules that need to be put in HW_AUTO */
- for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
- enable_clock_module(clk_modules_hw_auto_essential[i],
- MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
- wait_for_enable);
- };
-
- /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
- enable_clock_module(clk_modules_explicit_en_essential[i],
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
- wait_for_enable);
- };
-
- /* Put the clock domains in HW_AUTO mode now */
- for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
- enable_clock_domain(clk_domains_essential[i],
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- }
-}
-
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-static void enable_non_essential_clocks(void)
-{
- u32 i, max = 100, wait_for_enable = 0;
- u32 *const clk_domains_non_essential[] = {
- &prcm->cm_mpu_m3_clkstctrl,
- &prcm->cm_ivahd_clkstctrl,
- &prcm->cm_dsp_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sgx_clkstctrl,
- &prcm->cm1_abe_clkstctrl,
- &prcm->cm_c2c_clkstctrl,
- &prcm->cm_cam_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sdma_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_non_essential[] = {
- &prcm->cm_mpu_m3_mpu_m3_clkctrl,
- &prcm->cm_ivahd_ivahd_clkctrl,
- &prcm->cm_ivahd_sl2_clkctrl,
- &prcm->cm_dsp_dsp_clkctrl,
- &prcm->cm_l3_2_gpmc_clkctrl,
- &prcm->cm_l3instr_l3_3_clkctrl,
- &prcm->cm_l3instr_l3_instr_clkctrl,
- &prcm->cm_l3instr_intrconn_wp1_clkctrl,
- &prcm->cm_l3init_hsi_clkctrl,
- &prcm->cm_l3init_hsusbtll_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_non_essential[] = {
- &prcm->cm1_abe_aess_clkctrl,
- &prcm->cm1_abe_pdm_clkctrl,
- &prcm->cm1_abe_dmic_clkctrl,
- &prcm->cm1_abe_mcasp_clkctrl,
- &prcm->cm1_abe_mcbsp1_clkctrl,
- &prcm->cm1_abe_mcbsp2_clkctrl,
- &prcm->cm1_abe_mcbsp3_clkctrl,
- &prcm->cm1_abe_slimbus_clkctrl,
- &prcm->cm1_abe_timer5_clkctrl,
- &prcm->cm1_abe_timer6_clkctrl,
- &prcm->cm1_abe_timer7_clkctrl,
- &prcm->cm1_abe_timer8_clkctrl,
- &prcm->cm1_abe_wdt3_clkctrl,
- &prcm->cm_l4per_gptimer9_clkctrl,
- &prcm->cm_l4per_gptimer10_clkctrl,
- &prcm->cm_l4per_gptimer11_clkctrl,
- &prcm->cm_l4per_gptimer3_clkctrl,
- &prcm->cm_l4per_gptimer4_clkctrl,
- &prcm->cm_l4per_hdq1w_clkctrl,
- &prcm->cm_l4per_mcbsp4_clkctrl,
- &prcm->cm_l4per_mcspi2_clkctrl,
- &prcm->cm_l4per_mcspi3_clkctrl,
- &prcm->cm_l4per_mcspi4_clkctrl,
- &prcm->cm_l4per_mmcsd3_clkctrl,
- &prcm->cm_l4per_mmcsd4_clkctrl,
- &prcm->cm_l4per_mmcsd5_clkctrl,
- &prcm->cm_l4per_uart1_clkctrl,
- &prcm->cm_l4per_uart2_clkctrl,
- &prcm->cm_l4per_uart4_clkctrl,
- &prcm->cm_wkup_keyboard_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_cam_iss_clkctrl,
- &prcm->cm_cam_fdif_clkctrl,
- &prcm->cm_dss_dss_clkctrl,
- &prcm->cm_sgx_sgx_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
- &prcm->cm_l3init_fsusb_clkctrl,
- 0
- };
-
- /* Enable optional functional clock for ISS */
- setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable all optional functional clocks of DSS */
- setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
-
- /* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
- enable_clock_domain(clk_domains_non_essential[i],
- CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- }
-
- /* Clock modules that need to be put in HW_AUTO */
- for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
- enable_clock_module(clk_modules_hw_auto_non_essential[i],
- MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
- wait_for_enable);
- };
-
- /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
- i++) {
- enable_clock_module(clk_modules_explicit_en_non_essential[i],
- MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
- wait_for_enable);
- };
-
- /* Put the clock domains in HW_AUTO mode now */
- for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
- enable_clock_domain(clk_domains_non_essential[i],
- CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- }
-
- /* Put camera module in no sleep mode */
- clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
- CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
-
-
void freq_update_core(void)
{
u32 freq_config1 = 0;
CD_CLKCTRL_CLKTRCTRL_SHIFT);
}
+void setup_sri2c(void)
+{
+ u32 sys_clk_khz, cycles_hi, cycles_low, temp;
+
+ sys_clk_khz = get_sys_clk_freq() / 1000;
+
+ /*
+ * Setup the dedicated I2C controller for Voltage Control
+ * I2C clk - high period 40% low period 60%
+ */
+ cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+ cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+ /* values to be set in register - less by 5 & 7 respectively */
+ cycles_hi -= 5;
+ cycles_low -= 7;
+ temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+ (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+ writel(temp, &prcm->prm_vc_cfg_i2c_clk);
+
+ /* Disable high speed mode and all advanced features */
+ writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_hw_auto,
+ u32 *const *clk_modules_explicit_en,
+ u8 wait_for_enable)
+{
+ u32 i, max = 100;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i < max) && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in HW_AUTO */
+ for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
+ enable_clock_module(clk_modules_hw_auto[i],
+ MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+ wait_for_enable);
+ };
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
+
+ /* Put the clock domains in HW_AUTO mode now */
+ for (i = 0; (i < max) && clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+ }
+}
+
void prcm_init(void)
{
switch (omap_hw_init_context()) {
&dev_details.cs1_device_timings);
/* Calculate the register values */
- emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
+ emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
regs = &calculated_regs;
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
COBJS += sdram_elpida.o
COBJS += hwinit.o
+COBJS += clocks.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
--- /dev/null
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/gpio.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+#include <asm/omap_gpio.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
+
+struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
+
+const u32 sys_clk_array[8] = {
+ 12000000, /* 12 MHz */
+ 13000000, /* 13 MHz */
+ 16800000, /* 16.8 MHz */
+ 19200000, /* 19.2 MHz */
+ 26000000, /* 26 MHz */
+ 27000000, /* 27 MHz */
+ 38400000, /* 38.4 MHz */
+};
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
+static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
+ {230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
+static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+ {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
+ {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
+ {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
+ {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
+ {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
+ {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
+ {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+ {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
+ {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
+ {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
+ {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
+ {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
+ {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
+ {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+ {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
+ {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
+ {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
+ {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
+ {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
+ {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
+ {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+ {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
+ {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
+ {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
+ {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
+ {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
+ {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
+ {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+ {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
+ {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
+ {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
+ {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
+ {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
+ {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
+ {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
+ {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
+ {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+void setup_post_dividers(u32 *const base, const struct dpll_params *params)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ /* Setup post-dividers */
+ if (params->m2 >= 0)
+ writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+ if (params->m3 >= 0)
+ writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+ if (params->m4 >= 0)
+ writel(params->m4, &dpll_regs->cm_div_m4_dpll);
+ if (params->m5 >= 0)
+ writel(params->m5, &dpll_regs->cm_div_m5_dpll);
+ if (params->m6 >= 0)
+ writel(params->m6, &dpll_regs->cm_div_m6_dpll);
+ if (params->m7 >= 0)
+ writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+}
+
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0 : 600 MHz
+ * 4430 ES2.x : 792 MHz (OPP Turbo)
+ * 4460 : 920 MHz (OPP Turbo) - DCC disabled
+ */
+const struct dpll_params *get_mpu_dpll_params(void)
+{
+ u32 omap_rev, sysclk_ind;
+
+ omap_rev = omap_revision();
+ sysclk_ind = get_sys_clk_index();
+
+ if (omap_rev == OMAP4430_ES1_0)
+ return &mpu_dpll_params_1200mhz[sysclk_ind];
+ else if (omap_rev < OMAP4460_ES1_0)
+ return &mpu_dpll_params_1600mhz[sysclk_ind];
+ else
+ return &mpu_dpll_params_1840mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ switch (omap_revision()) {
+ case OMAP4430_ES1_0:
+ return &core_dpll_params_es1_1524mhz[sysclk_ind];
+ case OMAP4430_ES2_0:
+ case OMAP4430_SILICON_ID_INVALID:
+ /* safest */
+ return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
+ default:
+ return &core_dpll_params_1600mhz[sysclk_ind];
+ }
+}
+
+
+const struct dpll_params *get_per_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &per_dpll_params_1536mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_iva_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &iva_dpll_params_1862mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_usb_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &usb_dpll_params_1920mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_abe_dpll_params(void)
+{
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ u32 sysclk_ind = get_sys_clk_index();
+ return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+#else
+ return &abe_dpll_params_32k_196608khz;
+#endif
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+void scale_vcores(void)
+{
+ u32 volt, omap_rev;
+
+ setup_sri2c();
+
+ omap_rev = omap_revision();
+ /* TPS - supplies vdd_mpu on 4460 */
+ if (omap_rev >= OMAP4460_ES1_0) {
+ volt = 1313;
+ do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
+ }
+
+ /*
+ * VCORE 1
+ *
+ * 4430 : supplies vdd_mpu
+ * Setting a high voltage for Nitro mode as smart reflex is not enabled.
+ * We use the maximum possible value in the AVS range because the next
+ * higher voltage in the discrete range (code >= 0b111010) is way too
+ * high
+ *
+ * 4460 : supplies vdd_core
+ */
+ if (omap_rev < OMAP4460_ES1_0) {
+ volt = 1325;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+ } else {
+ volt = 1200;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+ }
+
+ /* VCORE 2 - supplies vdd_iva */
+ volt = 1200;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
+ /*
+ * VCORE 3
+ * 4430 : supplies vdd_core
+ * 4460 : not connected
+ */
+ if (omap_rev < OMAP4460_ES1_0) {
+ volt = 1200;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+ }
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 *const clk_domains_essential[] = {
+ &prcm->cm_l4per_clkstctrl,
+ &prcm->cm_l3init_clkstctrl,
+ &prcm->cm_memif_clkstctrl,
+ &prcm->cm_l4cfg_clkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_hw_auto_essential[] = {
+ &prcm->cm_wkup_gpio1_clkctrl,
+ &prcm->cm_l4per_gpio2_clkctrl,
+ &prcm->cm_l4per_gpio3_clkctrl,
+ &prcm->cm_l4per_gpio4_clkctrl,
+ &prcm->cm_l4per_gpio5_clkctrl,
+ &prcm->cm_l4per_gpio6_clkctrl,
+ &prcm->cm_memif_emif_1_clkctrl,
+ &prcm->cm_memif_emif_2_clkctrl,
+ &prcm->cm_l3init_hsusbotg_clkctrl,
+ &prcm->cm_l3init_usbphy_clkctrl,
+ &prcm->cm_l4cfg_l4_cfg_clkctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en_essential[] = {
+ &prcm->cm_l4per_gptimer2_clkctrl,
+ &prcm->cm_l3init_hsmmc1_clkctrl,
+ &prcm->cm_l3init_hsmmc2_clkctrl,
+ &prcm->cm_l4per_mcspi1_clkctrl,
+ &prcm->cm_wkup_gptimer1_clkctrl,
+ &prcm->cm_l4per_i2c1_clkctrl,
+ &prcm->cm_l4per_i2c2_clkctrl,
+ &prcm->cm_l4per_i2c3_clkctrl,
+ &prcm->cm_l4per_i2c4_clkctrl,
+ &prcm->cm_wkup_wdtimer2_clkctrl,
+ &prcm->cm_l4per_uart3_clkctrl,
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ /* Enable optional 48M functional clock for USB PHY */
+ setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
+ USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_non_essential_clocks(void)
+{
+ u32 *const clk_domains_non_essential[] = {
+ &prcm->cm_mpu_m3_clkstctrl,
+ &prcm->cm_ivahd_clkstctrl,
+ &prcm->cm_dsp_clkstctrl,
+ &prcm->cm_dss_clkstctrl,
+ &prcm->cm_sgx_clkstctrl,
+ &prcm->cm1_abe_clkstctrl,
+ &prcm->cm_c2c_clkstctrl,
+ &prcm->cm_cam_clkstctrl,
+ &prcm->cm_dss_clkstctrl,
+ &prcm->cm_sdma_clkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_hw_auto_non_essential[] = {
+ &prcm->cm_mpu_m3_mpu_m3_clkctrl,
+ &prcm->cm_ivahd_ivahd_clkctrl,
+ &prcm->cm_ivahd_sl2_clkctrl,
+ &prcm->cm_dsp_dsp_clkctrl,
+ &prcm->cm_l3_2_gpmc_clkctrl,
+ &prcm->cm_l3instr_l3_3_clkctrl,
+ &prcm->cm_l3instr_l3_instr_clkctrl,
+ &prcm->cm_l3instr_intrconn_wp1_clkctrl,
+ &prcm->cm_l3init_hsi_clkctrl,
+ &prcm->cm_l3init_hsusbtll_clkctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en_non_essential[] = {
+ &prcm->cm1_abe_aess_clkctrl,
+ &prcm->cm1_abe_pdm_clkctrl,
+ &prcm->cm1_abe_dmic_clkctrl,
+ &prcm->cm1_abe_mcasp_clkctrl,
+ &prcm->cm1_abe_mcbsp1_clkctrl,
+ &prcm->cm1_abe_mcbsp2_clkctrl,
+ &prcm->cm1_abe_mcbsp3_clkctrl,
+ &prcm->cm1_abe_slimbus_clkctrl,
+ &prcm->cm1_abe_timer5_clkctrl,
+ &prcm->cm1_abe_timer6_clkctrl,
+ &prcm->cm1_abe_timer7_clkctrl,
+ &prcm->cm1_abe_timer8_clkctrl,
+ &prcm->cm1_abe_wdt3_clkctrl,
+ &prcm->cm_l4per_gptimer9_clkctrl,
+ &prcm->cm_l4per_gptimer10_clkctrl,
+ &prcm->cm_l4per_gptimer11_clkctrl,
+ &prcm->cm_l4per_gptimer3_clkctrl,
+ &prcm->cm_l4per_gptimer4_clkctrl,
+ &prcm->cm_l4per_hdq1w_clkctrl,
+ &prcm->cm_l4per_mcbsp4_clkctrl,
+ &prcm->cm_l4per_mcspi2_clkctrl,
+ &prcm->cm_l4per_mcspi3_clkctrl,
+ &prcm->cm_l4per_mcspi4_clkctrl,
+ &prcm->cm_l4per_mmcsd3_clkctrl,
+ &prcm->cm_l4per_mmcsd4_clkctrl,
+ &prcm->cm_l4per_mmcsd5_clkctrl,
+ &prcm->cm_l4per_uart1_clkctrl,
+ &prcm->cm_l4per_uart2_clkctrl,
+ &prcm->cm_l4per_uart4_clkctrl,
+ &prcm->cm_wkup_keyboard_clkctrl,
+ &prcm->cm_wkup_wdtimer2_clkctrl,
+ &prcm->cm_cam_iss_clkctrl,
+ &prcm->cm_cam_fdif_clkctrl,
+ &prcm->cm_dss_dss_clkctrl,
+ &prcm->cm_sgx_sgx_clkctrl,
+ &prcm->cm_l3init_hsusbhost_clkctrl,
+ &prcm->cm_l3init_fsusb_clkctrl,
+ 0
+ };
+
+ /* Enable optional functional clock for ISS */
+ setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable all optional functional clocks of DSS */
+ setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+ do_enable_clocks(clk_domains_non_essential,
+ clk_modules_hw_auto_non_essential,
+ clk_modules_explicit_en_non_essential,
+ 0);
+
+ /* Put camera module in no sleep mode */
+ clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+ CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
--- /dev/null
+/*
+ *
+ * Clock initialization for OMAP5
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * Based on previous work by:
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+#include <asm/omap_gpio.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
+
+const u32 sys_clk_array[8] = {
+ 12000000, /* 12 MHz */
+ 0, /* NA */
+ 16800000, /* 16.8 MHz */
+ 19200000, /* 19.2 MHz */
+ 26000000, /* 26 MHz */
+ 0, /* NA */
+ 38400000, /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
+ {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
+ {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
+ {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
+ {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
+ {266, 2, 1, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {570, 8, 1, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
+ {665, 11, 1, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
+ {532, 12, 1, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {665, 23, 1, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
+ {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
+ {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
+ {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
+ {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
+ {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
+ {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
+ {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
+ {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
+ {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
+ {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
+ {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
+ {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
+ {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+void setup_post_dividers(u32 *const base, const struct dpll_params *params)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ /* Setup post-dividers */
+ if (params->m2 >= 0)
+ writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+ if (params->m3 >= 0)
+ writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+ if (params->h11 >= 0)
+ writel(params->h11, &dpll_regs->cm_div_h11_dpll);
+ if (params->h12 >= 0)
+ writel(params->h12, &dpll_regs->cm_div_h12_dpll);
+ if (params->h13 >= 0)
+ writel(params->h13, &dpll_regs->cm_div_h13_dpll);
+ if (params->h14 >= 0)
+ writel(params->h14, &dpll_regs->cm_div_h14_dpll);
+ if (params->h22 >= 0)
+ writel(params->h22, &dpll_regs->cm_div_h22_dpll);
+ if (params->h23 >= 0)
+ writel(params->h23, &dpll_regs->cm_div_h23_dpll);
+}
+
+const struct dpll_params *get_mpu_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &mpu_dpll_params_1100mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ /* Configuring the DDR to be at 532mhz */
+ return &core_dpll_params_2128mhz_ddr266[sysclk_ind];
+
+}
+
+const struct dpll_params *get_per_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &per_dpll_params_768mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_iva_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &iva_dpll_params_2330mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_usb_dpll_params(void)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &usb_dpll_params_1920mhz[sysclk_ind];
+}
+
+const struct dpll_params *get_abe_dpll_params(void)
+{
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ u32 sysclk_ind = get_sys_clk_index();
+ return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+#else
+ return &abe_dpll_params_32k_196608khz;
+#endif
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+void scale_vcores(void)
+{
+ u32 volt;
+
+ setup_sri2c();
+
+ /* Enable 1.22V from TPS for vdd_mpu */
+ volt = 1220;
+ do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
+
+ /* VCORE 1 - for vdd_core */
+ volt = 1000;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+
+ /* VCORE 2 - for vdd_MM */
+ volt = 1125;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 *const clk_domains_essential[] = {
+ &prcm->cm_l4per_clkstctrl,
+ &prcm->cm_l3init_clkstctrl,
+ &prcm->cm_memif_clkstctrl,
+ &prcm->cm_l4cfg_clkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_hw_auto_essential[] = {
+ &prcm->cm_wkup_gpio1_clkctrl,
+ &prcm->cm_l4per_gpio2_clkctrl,
+ &prcm->cm_l4per_gpio3_clkctrl,
+ &prcm->cm_l4per_gpio4_clkctrl,
+ &prcm->cm_l4per_gpio5_clkctrl,
+ &prcm->cm_l4per_gpio6_clkctrl,
+ &prcm->cm_memif_emif_1_clkctrl,
+ &prcm->cm_memif_emif_2_clkctrl,
+ &prcm->cm_l4cfg_l4_cfg_clkctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en_essential[] = {
+ &prcm->cm_l4per_gptimer2_clkctrl,
+ &prcm->cm_l3init_hsmmc1_clkctrl,
+ &prcm->cm_l3init_hsmmc2_clkctrl,
+ &prcm->cm_l4per_mcspi1_clkctrl,
+ &prcm->cm_wkup_gptimer1_clkctrl,
+ &prcm->cm_l4per_i2c1_clkctrl,
+ &prcm->cm_l4per_i2c2_clkctrl,
+ &prcm->cm_l4per_i2c3_clkctrl,
+ &prcm->cm_l4per_i2c4_clkctrl,
+ &prcm->cm_wkup_wdtimer2_clkctrl,
+ &prcm->cm_l4per_uart3_clkctrl,
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_non_essential_clocks(void)
+{
+ u32 *const clk_domains_non_essential[] = {
+ &prcm->cm_mpu_m3_clkstctrl,
+ &prcm->cm_ivahd_clkstctrl,
+ &prcm->cm_dsp_clkstctrl,
+ &prcm->cm_dss_clkstctrl,
+ &prcm->cm_sgx_clkstctrl,
+ &prcm->cm1_abe_clkstctrl,
+ &prcm->cm_c2c_clkstctrl,
+ &prcm->cm_cam_clkstctrl,
+ &prcm->cm_dss_clkstctrl,
+ &prcm->cm_sdma_clkstctrl,
+ 0
+ };
+
+ u32 *const clk_modules_hw_auto_non_essential[] = {
+ &prcm->cm_mpu_m3_mpu_m3_clkctrl,
+ &prcm->cm_ivahd_ivahd_clkctrl,
+ &prcm->cm_ivahd_sl2_clkctrl,
+ &prcm->cm_dsp_dsp_clkctrl,
+ &prcm->cm_l3_2_gpmc_clkctrl,
+ &prcm->cm_l3instr_l3_3_clkctrl,
+ &prcm->cm_l3instr_l3_instr_clkctrl,
+ &prcm->cm_l3instr_intrconn_wp1_clkctrl,
+ &prcm->cm_l3init_hsi_clkctrl,
+ &prcm->cm_l3init_hsusbtll_clkctrl,
+ 0
+ };
+
+ u32 *const clk_modules_explicit_en_non_essential[] = {
+ &prcm->cm1_abe_aess_clkctrl,
+ &prcm->cm1_abe_pdm_clkctrl,
+ &prcm->cm1_abe_dmic_clkctrl,
+ &prcm->cm1_abe_mcasp_clkctrl,
+ &prcm->cm1_abe_mcbsp1_clkctrl,
+ &prcm->cm1_abe_mcbsp2_clkctrl,
+ &prcm->cm1_abe_mcbsp3_clkctrl,
+ &prcm->cm1_abe_slimbus_clkctrl,
+ &prcm->cm1_abe_timer5_clkctrl,
+ &prcm->cm1_abe_timer6_clkctrl,
+ &prcm->cm1_abe_timer7_clkctrl,
+ &prcm->cm1_abe_timer8_clkctrl,
+ &prcm->cm1_abe_wdt3_clkctrl,
+ &prcm->cm_l4per_gptimer9_clkctrl,
+ &prcm->cm_l4per_gptimer10_clkctrl,
+ &prcm->cm_l4per_gptimer11_clkctrl,
+ &prcm->cm_l4per_gptimer3_clkctrl,
+ &prcm->cm_l4per_gptimer4_clkctrl,
+ &prcm->cm_l4per_hdq1w_clkctrl,
+ &prcm->cm_l4per_mcspi2_clkctrl,
+ &prcm->cm_l4per_mcspi3_clkctrl,
+ &prcm->cm_l4per_mcspi4_clkctrl,
+ &prcm->cm_l4per_mmcsd3_clkctrl,
+ &prcm->cm_l4per_mmcsd4_clkctrl,
+ &prcm->cm_l4per_mmcsd5_clkctrl,
+ &prcm->cm_l4per_uart1_clkctrl,
+ &prcm->cm_l4per_uart2_clkctrl,
+ &prcm->cm_l4per_uart4_clkctrl,
+ &prcm->cm_wkup_keyboard_clkctrl,
+ &prcm->cm_wkup_wdtimer2_clkctrl,
+ &prcm->cm_cam_iss_clkctrl,
+ &prcm->cm_cam_fdif_clkctrl,
+ &prcm->cm_dss_dss_clkctrl,
+ &prcm->cm_sgx_sgx_clkctrl,
+ &prcm->cm_l3init_hsusbhost_clkctrl,
+ &prcm->cm_l3init_fsusb_clkctrl,
+ 0
+ };
+
+ /* Enable optional functional clock for ISS */
+ setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable all optional functional clocks of DSS */
+ setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+ do_enable_clocks(clk_domains_non_essential,
+ clk_modules_hw_auto_non_essential,
+ clk_modules_explicit_en_non_essential,
+ 0);
+
+ /* Put camera module in no sleep mode */
+ clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+ CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
s8 m7;
};
+extern struct omap4_prcm_regs *const prcm;
+extern const u32 sys_clk_array[8];
+
+void scale_vcores(void);
+void do_scale_tps62361(u32 reg, u32 volt_mv);
+u32 omap_ddr_clk(void);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
+void setup_sri2c(void);
+void setup_post_dividers(u32 *const base, const struct dpll_params *params);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_non_essential_clocks(void);
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_hw_auto,
+ u32 *const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+const struct dpll_params *get_mpu_dpll_params(void);
+const struct dpll_params *get_core_dpll_params(void);
+const struct dpll_params *get_per_dpll_params(void);
+const struct dpll_params *get_iva_dpll_params(void);
+const struct dpll_params *get_usb_dpll_params(void);
+const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP4_H_ */
};
extern const struct omap_sysinfo sysinfo;
-extern struct omap4_prcm_regs *const prcm;
-
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP5_H_
+#define _CLOCKS_OMAP5_H_
+#include <common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY 1000000
+
+#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
+#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
+#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
+#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
+
+struct omap5_prcm_regs {
+ /* cm1.ckgen */
+ u32 cm_clksel_core; /* 4a004100 */
+ u32 pad001[1]; /* 4a004104 */
+ u32 cm_clksel_abe; /* 4a004108 */
+ u32 pad002[1]; /* 4a00410c */
+ u32 cm_dll_ctrl; /* 4a004110 */
+ u32 pad003[3]; /* 4a004114 */
+ u32 cm_clkmode_dpll_core; /* 4a004120 */
+ u32 cm_idlest_dpll_core; /* 4a004124 */
+ u32 cm_autoidle_dpll_core; /* 4a004128 */
+ u32 cm_clksel_dpll_core; /* 4a00412c */
+ u32 cm_div_m2_dpll_core; /* 4a004130 */
+ u32 cm_div_m3_dpll_core; /* 4a004134 */
+ u32 cm_div_h11_dpll_core; /* 4a004138 */
+ u32 cm_div_h12_dpll_core; /* 4a00413c */
+ u32 cm_div_h13_dpll_core; /* 4a004140 */
+ u32 cm_div_h14_dpll_core; /* 4a004144 */
+ u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */
+ u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */
+ u32 cm_emu_override_dpll_core; /* 4a004150 */
+
+ u32 cm_div_h22_dpllcore; /* 4a004154 */
+ u32 cm_div_h23_dpll_core; /* 4a004158 */
+ u32 pad0041[1]; /* 4a00415c */
+ u32 cm_clkmode_dpll_mpu; /* 4a004160 */
+ u32 cm_idlest_dpll_mpu; /* 4a004164 */
+ u32 cm_autoidle_dpll_mpu; /* 4a004168 */
+ u32 cm_clksel_dpll_mpu; /* 4a00416c */
+ u32 cm_div_m2_dpll_mpu; /* 4a004170 */
+ u32 pad005[5]; /* 4a004174 */
+ u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */
+ u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */
+ u32 pad006[3]; /* 4a004190 */
+ u32 cm_bypclk_dpll_mpu; /* 4a00419c */
+ u32 cm_clkmode_dpll_iva; /* 4a0041a0 */
+ u32 cm_idlest_dpll_iva; /* 4a0041a4 */
+ u32 cm_autoidle_dpll_iva; /* 4a0041a8 */
+ u32 cm_clksel_dpll_iva; /* 4a0041ac */
+ u32 pad007[2]; /* 4a0041b0 */
+ u32 cm_div_h11_dpll_iva; /* 4a0041b8 */
+ u32 cm_div_h12_dpll_iva; /* 4a0041bc */
+ u32 pad008[2]; /* 4a0041c0 */
+ u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */
+ u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */
+ u32 pad009[3]; /* 4a0041d0 */
+ u32 cm_bypclk_dpll_iva; /* 4a0041dc */
+ u32 cm_clkmode_dpll_abe; /* 4a0041e0 */
+ u32 cm_idlest_dpll_abe; /* 4a0041e4 */
+ u32 cm_autoidle_dpll_abe; /* 4a0041e8 */
+ u32 cm_clksel_dpll_abe; /* 4a0041ec */
+ u32 cm_div_m2_dpll_abe; /* 4a0041f0 */
+ u32 cm_div_m3_dpll_abe; /* 4a0041f4 */
+ u32 pad010[4]; /* 4a0041f8 */
+ u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */
+ u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */
+ u32 pad011[4]; /* 4a004210 */
+ u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */
+ u32 cm_idlest_dpll_ddrphy; /* 4a004224 */
+ u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */
+ u32 cm_clksel_dpll_ddrphy; /* 4a00422c */
+ u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */
+ u32 pad012[1]; /* 4a004234 */
+ u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */
+ u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */
+ u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */
+ u32 pad013[1]; /* 4a004244 */
+ u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */
+ u32 pad014[5]; /* 4a00424c */
+ u32 cm_shadow_freq_config1; /* 4a004260 */
+ u32 pad0141[47]; /* 4a004264 */
+ u32 cm_mpu_mpu_clkctrl; /* 4a004320 */
+
+
+ /* cm1.dsp */
+ u32 pad015[55]; /* 4a004324 */
+ u32 cm_dsp_clkstctrl; /* 4a004400 */
+ u32 pad016[7]; /* 4a004404 */
+ u32 cm_dsp_dsp_clkctrl; /* 4a004420 */
+
+ /* cm1.abe */
+ u32 pad017[55]; /* 4a004424 */
+ u32 cm1_abe_clkstctrl; /* 4a004500 */
+ u32 pad018[7]; /* 4a004504 */
+ u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */
+ u32 pad019[1]; /* 4a004524 */
+ u32 cm1_abe_aess_clkctrl; /* 4a004528 */
+ u32 pad020[1]; /* 4a00452c */
+ u32 cm1_abe_pdm_clkctrl; /* 4a004530 */
+ u32 pad021[1]; /* 4a004534 */
+ u32 cm1_abe_dmic_clkctrl; /* 4a004538 */
+ u32 pad022[1]; /* 4a00453c */
+ u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */
+ u32 pad023[1]; /* 4a004544 */
+ u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */
+ u32 pad024[1]; /* 4a00454c */
+ u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */
+ u32 pad025[1]; /* 4a004554 */
+ u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */
+ u32 pad026[1]; /* 4a00455c */
+ u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */
+ u32 pad027[1]; /* 4a004564 */
+ u32 cm1_abe_timer5_clkctrl; /* 4a004568 */
+ u32 pad028[1]; /* 4a00456c */
+ u32 cm1_abe_timer6_clkctrl; /* 4a004570 */
+ u32 pad029[1]; /* 4a004574 */
+ u32 cm1_abe_timer7_clkctrl; /* 4a004578 */
+ u32 pad030[1]; /* 4a00457c */
+ u32 cm1_abe_timer8_clkctrl; /* 4a004580 */
+ u32 pad031[1]; /* 4a004584 */
+ u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */
+
+ /* cm2.ckgen */
+ u32 pad032[3805]; /* 4a00458c */
+ u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */
+ u32 cm_clksel_usb_60mhz; /* 4a008104 */
+ u32 cm_scale_fclk; /* 4a008108 */
+ u32 pad033[1]; /* 4a00810c */
+ u32 cm_core_dvfs_perf1; /* 4a008110 */
+ u32 cm_core_dvfs_perf2; /* 4a008114 */
+ u32 cm_core_dvfs_perf3; /* 4a008118 */
+ u32 cm_core_dvfs_perf4; /* 4a00811c */
+ u32 pad034[1]; /* 4a008120 */
+ u32 cm_core_dvfs_current; /* 4a008124 */
+ u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */
+ u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */
+ u32 cm_iva_dvfs_perf_abe; /* 4a008130 */
+ u32 pad035[1]; /* 4a008134 */
+ u32 cm_iva_dvfs_current; /* 4a008138 */
+ u32 pad036[1]; /* 4a00813c */
+ u32 cm_clkmode_dpll_per; /* 4a008140 */
+ u32 cm_idlest_dpll_per; /* 4a008144 */
+ u32 cm_autoidle_dpll_per; /* 4a008148 */
+ u32 cm_clksel_dpll_per; /* 4a00814c */
+ u32 cm_div_m2_dpll_per; /* 4a008150 */
+ u32 cm_div_m3_dpll_per; /* 4a008154 */
+ u32 cm_div_h11_dpll_per; /* 4a008158 */
+ u32 cm_div_h12_dpll_per; /* 4a00815c */
+ u32 pad0361[1]; /* 4a008160 */
+ u32 cm_div_h14_dpll_per; /* 4a008164 */
+ u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */
+ u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */
+ u32 cm_emu_override_dpll_per; /* 4a008170 */
+ u32 pad037[3]; /* 4a008174 */
+ u32 cm_clkmode_dpll_usb; /* 4a008180 */
+ u32 cm_idlest_dpll_usb; /* 4a008184 */
+ u32 cm_autoidle_dpll_usb; /* 4a008188 */
+ u32 cm_clksel_dpll_usb; /* 4a00818c */
+ u32 cm_div_m2_dpll_usb; /* 4a008190 */
+ u32 pad038[5]; /* 4a008194 */
+ u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */
+ u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */
+ u32 pad039[1]; /* 4a0081b0 */
+ u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */
+ u32 pad040[2]; /* 4a0081b8 */
+ u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */
+ u32 cm_idlest_dpll_unipro; /* 4a0081c4 */
+ u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */
+ u32 cm_clksel_dpll_unipro; /* 4a0081cc */
+ u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */
+ u32 pad041[5]; /* 4a0081d4 */
+ u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */
+ u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */
+
+ /* cm2.core */
+ u32 pad0411[324]; /* 4a0081f0 */
+ u32 cm_l3_1_clkstctrl; /* 4a008700 */
+ u32 pad042[1]; /* 4a008704 */
+ u32 cm_l3_1_dynamicdep; /* 4a008708 */
+ u32 pad043[5]; /* 4a00870c */
+ u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */
+ u32 pad044[55]; /* 4a008724 */
+ u32 cm_l3_2_clkstctrl; /* 4a008800 */
+ u32 pad045[1]; /* 4a008804 */
+ u32 cm_l3_2_dynamicdep; /* 4a008808 */
+ u32 pad046[5]; /* 4a00880c */
+ u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */
+ u32 pad047[1]; /* 4a008824 */
+ u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */
+ u32 pad048[1]; /* 4a00882c */
+ u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */
+ u32 pad049[51]; /* 4a008834 */
+ u32 cm_mpu_m3_clkstctrl; /* 4a008900 */
+ u32 cm_mpu_m3_staticdep; /* 4a008904 */
+ u32 cm_mpu_m3_dynamicdep; /* 4a008908 */
+ u32 pad050[5]; /* 4a00890c */
+ u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */
+ u32 pad051[55]; /* 4a008924 */
+ u32 cm_sdma_clkstctrl; /* 4a008a00 */
+ u32 cm_sdma_staticdep; /* 4a008a04 */
+ u32 cm_sdma_dynamicdep; /* 4a008a08 */
+ u32 pad052[5]; /* 4a008a0c */
+ u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */
+ u32 pad053[55]; /* 4a008a24 */
+ u32 cm_memif_clkstctrl; /* 4a008b00 */
+ u32 pad054[7]; /* 4a008b04 */
+ u32 cm_memif_dmm_clkctrl; /* 4a008b20 */
+ u32 pad055[1]; /* 4a008b24 */
+ u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */
+ u32 pad056[1]; /* 4a008b2c */
+ u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */
+ u32 pad057[1]; /* 4a008b34 */
+ u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */
+ u32 pad058[1]; /* 4a008b3c */
+ u32 cm_memif_dll_clkctrl; /* 4a008b40 */
+ u32 pad059[3]; /* 4a008b44 */
+ u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */
+ u32 pad060[1]; /* 4a008b54 */
+ u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */
+ u32 pad061[1]; /* 4a008b5c */
+ u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */
+ u32 pad062[39]; /* 4a008b64 */
+ u32 cm_c2c_clkstctrl; /* 4a008c00 */
+ u32 cm_c2c_staticdep; /* 4a008c04 */
+ u32 cm_c2c_dynamicdep; /* 4a008c08 */
+ u32 pad063[5]; /* 4a008c0c */
+ u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */
+ u32 pad064[1]; /* 4a008c24 */
+ u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */
+ u32 pad065[1]; /* 4a008c2c */
+ u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */
+ u32 pad066[51]; /* 4a008c34 */
+ u32 cm_l4cfg_clkstctrl; /* 4a008d00 */
+ u32 pad067[1]; /* 4a008d04 */
+ u32 cm_l4cfg_dynamicdep; /* 4a008d08 */
+ u32 pad068[5]; /* 4a008d0c */
+ u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */
+ u32 pad069[1]; /* 4a008d24 */
+ u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */
+ u32 pad070[1]; /* 4a008d2c */
+ u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */
+ u32 pad071[1]; /* 4a008d34 */
+ u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */
+ u32 pad072[49]; /* 4a008d3c */
+ u32 cm_l3instr_clkstctrl; /* 4a008e00 */
+ u32 pad073[7]; /* 4a008e04 */
+ u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */
+ u32 pad074[1]; /* 4a008e24 */
+ u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */
+ u32 pad075[5]; /* 4a008e2c */
+ u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */
+
+
+ /* cm2.ivahd */
+ u32 pad076[47]; /* 4a008e44 */
+ u32 cm_ivahd_clkstctrl; /* 4a008f00 */
+ u32 pad077[7]; /* 4a008f04 */
+ u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */
+ u32 pad078[1]; /* 4a008f24 */
+ u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */
+
+ /* cm2.cam */
+ u32 pad079[53]; /* 4a008f2c */
+ u32 cm_cam_clkstctrl; /* 4a009000 */
+ u32 pad080[7]; /* 4a009004 */
+ u32 cm_cam_iss_clkctrl; /* 4a009020 */
+ u32 pad081[1]; /* 4a009024 */
+ u32 cm_cam_fdif_clkctrl; /* 4a009028 */
+
+ /* cm2.dss */
+ u32 pad082[53]; /* 4a00902c */
+ u32 cm_dss_clkstctrl; /* 4a009100 */
+ u32 pad083[7]; /* 4a009104 */
+ u32 cm_dss_dss_clkctrl; /* 4a009120 */
+
+ /* cm2.sgx */
+ u32 pad084[55]; /* 4a009124 */
+ u32 cm_sgx_clkstctrl; /* 4a009200 */
+ u32 pad085[7]; /* 4a009204 */
+ u32 cm_sgx_sgx_clkctrl; /* 4a009220 */
+
+ /* cm2.l3init */
+ u32 pad086[55]; /* 4a009224 */
+ u32 cm_l3init_clkstctrl; /* 4a009300 */
+
+ /* cm2.l3init */
+ u32 pad087[9]; /* 4a009304 */
+ u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */
+ u32 pad088[1]; /* 4a00932c */
+ u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */
+ u32 pad089[1]; /* 4a009334 */
+ u32 cm_l3init_hsi_clkctrl; /* 4a009338 */
+ u32 pad090[7]; /* 4a00933c */
+ u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */
+ u32 pad091[1]; /* 4a00935c */
+ u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */
+ u32 pad092[1]; /* 4a009364 */
+ u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */
+ u32 pad093[3]; /* 4a00936c */
+ u32 cm_l3init_p1500_clkctrl; /* 4a009378 */
+ u32 pad094[21]; /* 4a00937c */
+ u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */
+ u32 pad095[3]; /* 4a0093d4 */
+ u32 cm_l3init_ocp2scp1_clkctrl;
+
+ /* cm2.l4per */
+ u32 pad096[7]; /* 4a0093e4 */
+ u32 cm_l4per_clkstctrl; /* 4a009400 */
+ u32 pad097[1]; /* 4a009404 */
+ u32 cm_l4per_dynamicdep; /* 4a009408 */
+ u32 pad098[5]; /* 4a00940c */
+ u32 cm_l4per_adc_clkctrl; /* 4a009420 */
+ u32 pad100[1]; /* 4a009424 */
+ u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */
+ u32 pad101[1]; /* 4a00942c */
+ u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */
+ u32 pad102[1]; /* 4a009434 */
+ u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */
+ u32 pad103[1]; /* 4a00943c */
+ u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */
+ u32 pad104[1]; /* 4a009444 */
+ u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */
+ u32 pad105[1]; /* 4a00944c */
+ u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */
+ u32 pad106[1]; /* 4a009454 */
+ u32 cm_l4per_elm_clkctrl; /* 4a009458 */
+ u32 pad107[1]; /* 4a00945c */
+ u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */
+ u32 pad108[1]; /* 4a009464 */
+ u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */
+ u32 pad109[1]; /* 4a00946c */
+ u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */
+ u32 pad110[1]; /* 4a009474 */
+ u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */
+ u32 pad111[1]; /* 4a00947c */
+ u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */
+ u32 pad112[1]; /* 4a009484 */
+ u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */
+ u32 pad113[1]; /* 4a00948c */
+ u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */
+ u32 pad114[1]; /* 4a009494 */
+ u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */
+ u32 pad115[1]; /* 4a00949c */
+ u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */
+ u32 pad116[1]; /* 4a0094a4 */
+ u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */
+ u32 pad117[1]; /* 4a0094ac */
+ u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */
+ u32 pad118[1]; /* 4a0094b4 */
+ u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */
+ u32 pad119[1]; /* 4a0094bc */
+ u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */
+ u32 pad1191[3]; /* 4a0094c4 */
+ u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */
+ u32 pad120[1]; /* 4a0094d4 */
+ u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */
+ u32 pad121[3]; /* 4a0094dc */
+ u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */
+ u32 pad123[1]; /* 4a0094ec */
+ u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */
+ u32 pad124[1]; /* 4a0094f4 */
+ u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */
+ u32 pad125[1]; /* 4a0094fc */
+ u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */
+ u32 pad126[1]; /* 4a009504 */
+ u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */
+ u32 pad127[1]; /* 4a00950c */
+ u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */
+ u32 pad1271[1]; /* 4a009514 */
+ u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */
+ u32 pad1272[1]; /* 4a00951c */
+ u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */
+ u32 pad128[1]; /* 4a009524 */
+ u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */
+ u32 pad129[1]; /* 4a00952c */
+ u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */
+ u32 pad130[1]; /* 4a009534 */
+ u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */
+ u32 pad131[1]; /* 4a00953c */
+ u32 cm_l4per_uart1_clkctrl; /* 4a009540 */
+ u32 pad132[1]; /* 4a009544 */
+ u32 cm_l4per_uart2_clkctrl; /* 4a009548 */
+ u32 pad133[1]; /* 4a00954c */
+ u32 cm_l4per_uart3_clkctrl; /* 4a009550 */
+ u32 pad134[1]; /* 4a009554 */
+ u32 cm_l4per_uart4_clkctrl; /* 4a009558 */
+ u32 pad135[1]; /* 4a00955c */
+ u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */
+ u32 pad136[1]; /* 4a009564 */
+ u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */
+ u32 pad1371[1]; /* 4a00956c */
+ u32 cm_l4per_uart5_clkctrl; /* 4a009570 */
+ u32 pad1372[1]; /* 4a009574 */
+ u32 cm_l4per_uart6_clkctrl; /* 4a009578 */
+ u32 pad1374[1]; /* 4a00957c */
+ u32 cm_l4sec_clkstctrl; /* 4a009580 */
+ u32 cm_l4sec_staticdep; /* 4a009584 */
+ u32 cm_l4sec_dynamicdep; /* 4a009588 */
+ u32 pad138[5]; /* 4a00958c */
+ u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */
+ u32 pad139[1]; /* 4a0095a4 */
+ u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */
+ u32 pad140[1]; /* 4a0095ac */
+ u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */
+ u32 pad141[1]; /* 4a0095b4 */
+ u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */
+ u32 pad142[1]; /* 4a0095bc */
+ u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */
+ u32 pad143[1]; /* 4a0095c4 */
+ u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */
+ u32 pad144[3]; /* 4a0095cc */
+ u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */
+ u32 pad145[3660425]; /* 4a0095dc */
+
+ /* l4 wkup regs */
+ u32 pad201[6211]; /* 4ae00000 */
+ u32 cm_abe_pll_ref_clksel; /* 4ae0610c */
+ u32 cm_sys_clksel; /* 4ae06110 */
+ u32 pad202[1467]; /* 4ae06114 */
+ u32 cm_wkup_clkstctrl; /* 4ae07800 */
+ u32 pad203[7]; /* 4ae07804 */
+ u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */
+ u32 pad204; /* 4ae07824 */
+ u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */
+ u32 pad205; /* 4ae0782c */
+ u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */
+ u32 pad206; /* 4ae07834 */
+ u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */
+ u32 pad207; /* 4ae0783c */
+ u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */
+ u32 pad208; /* 4ae07844 */
+ u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */
+ u32 pad209; /* 4ae0784c */
+ u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */
+ u32 pad210; /* 4ae07854 */
+ u32 cm_wkup_usim_clkctrl; /* 4ae07858 */
+ u32 pad211; /* 4ae0785c */
+ u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */
+ u32 pad212[5]; /* 4ae07864 */
+ u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */
+ u32 pad213; /* 4ae0787c */
+ u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */
+ u32 pad214; /* 4ae07884 */
+ u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */
+ u32 pad215[197]; /* 4ae0788c */
+ u32 prm_vc_val_bypass; /* 4ae07ba0 */
+ u32 pad216[4];
+ u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
+ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
+};
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL 0
+#define CM_IDLEST_DPLL 0x4
+#define CM_AUTOIDLE_DPLL 0x8
+#define CM_CLKSEL_DPLL 0xC
+
+#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
+
+#define DPLL_EN_STOP 1
+#define DPLL_EN_MN_BYPASS 4
+#define DPLL_EN_LOW_POWER_BYPASS 5
+#define DPLL_EN_FAST_RELOCK_BYPASS 6
+#define DPLL_EN_LOCK 7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK 1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT 8
+#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT 0
+#define CM_CLKSEL_DPLL_N_MASK 0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT 22
+#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
+
+#define OMAP4_DPLL_MAX_N 127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT 0
+#define CLKSEL_L3_SHIFT 4
+#define CLKSEL_L4_SHIFT 8
+
+#define CLKSEL_CORE_X2_DIV_1 0
+#define CLKSEL_L3_CORE_DIV_2 1
+#define CLKSEL_L4_L3_DIV_2 1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
+#define CD_CLKCTRL_CLKTRCTRL_MASK 3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
+#define MODULE_CLKCTRL_MODULEMODE_MASK 3
+#define MODULE_CLKCTRL_IDLEST_SHIFT 16
+#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
+#define MODULE_CLKCTRL_IDLEST_IDLE 2
+#define MODULE_CLKCTRL_IDLEST_DISABLED 3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
+#define OMAP_SYS_CLK_IND_38_4_MHZ 6
+#define OMAP_32K_CLK_FREQ 32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
+#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
+
+/* SMPS */
+#define SMPS_I2C_SLAVE_ADDR 0x12
+#define SMPS_REG_ADDR_VCORE1 0x55
+#define SMPS_REG_ADDR_VCORE2 0x5B
+#define SMPS_REG_ADDR_VCORE3 0x61
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR 0x60
+#define TPS62361_REG_ADDR_SET0 0x0
+#define TPS62361_REG_ADDR_SET1 0x1
+#define TPS62361_REG_ADDR_SET2 0x2
+#define TPS62361_REG_ADDR_SET3 0x3
+#define TPS62361_REG_ADDR_CTRL 0x4
+#define TPS62361_REG_ADDR_TEMP 0x5
+#define TPS62361_REG_ADDR_RMP_CTRL 0x6
+#define TPS62361_REG_ADDR_CHIP_ID 0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
+
+#define TPS62361_BASE_VOLT_MV 500
+#define TPS62361_VSEL0_GPIO 7
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
+
+#define DPLL_NO_LOCK 0
+#define DPLL_LOCK 1
+
+#define NUM_SYS_CLKS 7
+
+struct dpll_regs {
+ u32 cm_clkmode_dpll;
+ u32 cm_idlest_dpll;
+ u32 cm_autoidle_dpll;
+ u32 cm_clksel_dpll;
+ u32 cm_div_m2_dpll;
+ u32 cm_div_m3_dpll;
+ u32 cm_div_h11_dpll;
+ u32 cm_div_h12_dpll;
+ u32 cm_div_h13_dpll;
+ u32 cm_div_h14_dpll;
+ u32 reserved[2];
+ u32 cm_div_h22_dpll;
+ u32 cm_div_h23_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+ u32 m;
+ u32 n;
+ u8 m2;
+ u8 m3;
+ u8 h11;
+ u8 h12;
+ u8 h13;
+ u8 h14;
+ u8 h22;
+ u8 h23;
+};
+
+extern struct omap5_prcm_regs *const prcm;
+extern const u32 sys_clk_array[8];
+
+void scale_vcores(void);
+void do_scale_tps62361(u32 reg, u32 volt_mv);
+u32 omap_ddr_clk(void);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
+void setup_sri2c(void);
+void setup_post_dividers(u32 *const base, const struct dpll_params *params);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_non_essential_clocks(void);
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_hw_auto,
+ u32 *const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+const struct dpll_params *get_mpu_dpll_params(void);
+const struct dpll_params *get_core_dpll_params(void);
+const struct dpll_params *get_per_dpll_params(void);
+const struct dpll_params *get_iva_dpll_params(void);
+const struct dpll_params *get_usb_dpll_params(void);
+const struct dpll_params *get_abe_dpll_params(void);
+#endif /* _CLOCKS_OMAP5_H_ */
#include <asm/arch/clocks.h>
#include <asm/omap_common.h>
#include <asm/arch/mux_omap5.h>
+#include <asm/arch/clocks.h>
struct omap_sysinfo {
char *board_string;
};
extern const struct omap_sysinfo sysinfo;
-extern struct omap5_prcm_regs *const prcm;
-
void gpmc_init(void);
void watchdog_init(void);
u32 get_device_type(void);
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