pinctrl: renesas: Synchronize R8A77995 D3 PFC tables with Linux 6.5.3

Synchronize R-Car R8A77995 D3 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 06caf16c991820c24ba9feb7044863b6e607caa8..c0d69937ddb4dbd2fcf8152e4184c901f9a58c29 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -23,7 +23,7 @@
        PORT_GP_CFG_9(0,  fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
-       PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
+       PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
        PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
@@ -36,7 +36,8 @@
        PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),           \
        PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),           \
        PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),           \
-       PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+       PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP),      \
+       PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
 
 /*
  * F_() : just information
@@ -2854,19 +2855,37 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL1_26
                /* RESERVED 25-0 */ ))
        },
-       { },
+       { /* sentinel */ }
+};
+
+enum ioctrl_regs {
+       POCCTRL0,
+       POCCTRL2,
+       TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+       [POCCTRL0] = { 0xe6060380, },
+       [POCCTRL2] = { 0xe6060388, },
+       [TDSELCTRL] = { 0xe60603c0, },
+       { /* sentinel */ }
 };
 
+
 static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
-       int bit = -EINVAL;
-
-       *pocctrl = 0xe6060380;
+       switch (pin) {
+       case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+               return 29 - (pin - RCAR_GP_PIN(3, 0));
 
-       if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
-               bit = 29 - (pin - RCAR_GP_PIN(3, 0));
+       case PIN_VDDQ_AVB0:
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+               return 0;
 
-       return bit;
+       default:
+               return -EINVAL;
+       }
 }
 
 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -3077,15 +3096,6 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
        { /* sentinel */ }
 };
 
-enum ioctrl_regs {
-       TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
-       [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
-};
-
 static const struct pinmux_bias_reg *
 r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
                         unsigned int *puen_bit, unsigned int *pud_bit)