ARM: imx: imx8m: Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options

Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options for iMX8M SoCs
in case they should be operated faster, e.g. to improve boot time.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 2ca3bf68e742bd9d9dc8e7d4694f8ce490bbc844..76132defc21c455804f199ae1285647548158646 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -248,6 +248,26 @@ int intpll_configure(enum pll_clocks pll, ulong freq)
                pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
                        INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
                break;
+       case MHZ(1400):
+               /* 24 * 0x15e / 3 / 2 ^ 1 */
+               pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x15e) |
+                       INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+               break;
+       case MHZ(1500):
+               /* 24 * 0x177 / 3 / 2 ^ 1 */
+               pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x177) |
+                       INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+               break;
+       case MHZ(1600):
+               /* 24 * 0xc8 / 3 / 2 ^ 0 */
+               pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
+                       INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
+               break;
+       case MHZ(1800):
+               /* 24 * 0xe1 / 3 / 2 ^ 0 */
+               pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xe1) |
+                       INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
+               break;
        case MHZ(2000):
                /* 24 * 0xfa / 3 / 2 ^ 0 */
                pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |