fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after resetting the controller

eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.

Signed-off-by: P.V.Suresh <pala@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a368fe60db4a285bb5b43a8ec16069ab8e436d24..57cd4ee1f436cced7b367e09e5b43c200ab54ca5 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -384,10 +384,6 @@ static int esdhc_init(struct mmc *mmc)
        int ret = 0;
        u8 card_absent;
 
-       /* Enable cache snooping */
-       if (cfg && !cfg->no_snoop)
-               esdhc_write32(&regs->scr, 0x00000040);
-
        /* Reset the entire host controller */
        esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 
@@ -395,6 +391,10 @@ static int esdhc_init(struct mmc *mmc)
        while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
                udelay(1000);
 
+       /* Enable cache snooping */
+       if (cfg && !cfg->no_snoop)
+               esdhc_write32(&regs->scr, 0x00000040);
+
        esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 
        /* Set the initial clock speed */