ARM: socfpga: Configure PL310 latencies

Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index e1adea143cf65c8393aec469c8a02d12fc43e424..fcf211d62bd628e3a7b10f58ea66e05c7460f3dd 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -62,6 +62,9 @@ void v7_outer_cache_enable(void)
        /* Disable the L2 cache */
        clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
+       writel(0x111, &pl310->pl310_tag_latency_ctrl);
+       writel(0x121, &pl310->pl310_data_latency_ctrl);
+
        /* enable BRESP, instruction and data prefetch, full line of zeroes */
        setbits_le32(&pl310->pl310_aux_ctrl,
                     L310_AUX_CTRL_DATA_PREFETCH_MASK |