board: sl28: fix RGMII clock and voltage

It was noticed that the clock isn't continuously enabled when there is
no link. This is because the 125MHz clock is derived from the internal
PLL which seems to go into some kind of power-down mode every once in a
while. The LS1028A expects a contiuous clock. Thus enable the PLL all
the time.

Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is
the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO
regulator.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
index fe708bdbfa06d8c4a1559208df9d8d8f4a56c432..33d85ed83a60563b7342a4a1128646e0047fe185 100644 (file)
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
@@ -41,8 +41,9 @@
 
                qca,clk-out-frequency = <125000000>;
                qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+               qca,keep-pll-enabled;
 
-               vddio-supply = <&vddh>;
+               vddio-supply = <&vddio>;
 
                vddio: vddio-regulator {
                        regulator-name = "VDDIO";

diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
index 33b16303adb191d891c971eedeaffa2a2c4947cc..b95e082b70ba973e749dc2b2957e749177c3ce45 100644 (file)
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
@@ -32,8 +32,9 @@
 
                qca,clk-out-frequency = <125000000>;
                qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+               qca,keep-pll-enabled;
 
-               vddio-supply = <&vddh>;
+               vddio-supply = <&vddio>;
 
                vddio: vddio-regulator {
                        regulator-name = "VDDIO";