]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit
authorAlison Wang <b18965@freescale.com>
Wed, 15 Jul 2015 07:13:05 +0000 (15:13 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 30 Nov 2015 16:53:01 +0000 (08:53 -0800)
This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot.  Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.  This causes the timer compare to fire 344 seconds
after u-boot configures it.  Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains.  Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/cpu/armv7/ls102xa/timer.c
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

index 11b17b2c748aa60e937e184fb4cc84f99653602a..e6a32caafc672014505ab6e1c87ebb2f4cbe1fd9 100644 (file)
@@ -56,7 +56,8 @@ static inline unsigned long long us_to_tick(unsigned long long usec)
 int timer_init(void)
 {
        struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
-       unsigned long ctrl, val, freq;
+       unsigned long ctrl, freq;
+       unsigned long long val;
 
        /* Enable System Counter */
        writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
index 09ed9809f11606d2f3f75dce34a0d931dfef7f40..1bcdf04dd4847bca0e7c39bc2d9106baa7a56ad7 100644 (file)
@@ -31,7 +31,7 @@
 #define RCWSR4_SRDS1_PRTCL_SHIFT       24
 #define RCWSR4_SRDS1_PRTCL_MASK                0xff000000
 
-#define TIMER_COMP_VAL                 0xffffffff
+#define TIMER_COMP_VAL                 0xffffffffffffffffull
 #define ARCH_TIMER_CTRL_ENABLE         (1 << 0)
 #define SYS_COUNTER_CTRL_ENABLE                (1 << 24)