if (set)
reg |= BIT(gate->bit_idx);
} else {
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ reg = gate->io_gate_val;
+#else
reg = readl(gate->reg);
+#endif
if (set)
reg |= BIT(gate->bit_idx);
dev_get_clk_ptr(clk->dev) : clk);
u32 reg;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ reg = gate->io_gate_val;
+#else
reg = readl(gate->reg);
+#endif
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
gate->reg = reg;
gate->bit_idx = bit_idx;
gate->flags = clk_gate_flags;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+ gate->io_gate_val = *(u32 *)reg;
+#endif
clk = &gate->clk;