ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist

The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 9518392cddb7f327c292fb089070718ea1a9a1ec..d1e659b46b0b271ad01ec0a58662101c6bce1789 100644 (file)
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -43,7 +43,6 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #define CONFIG_SYS_DDR_MODE_CONTROL    0x00000000
 #define CONFIG_SYS_DDR_ZQ_CONTROL      0x00000000
 #define CONFIG_SYS_DDR_WRLVL_CONTROL   0x00000000
-#define CONFIG_SYS_DDR_PD_CONTROL      0x00000000
 #define CONFIG_SYS_DDR_SR_CNTR         0x00000000
 #define CONFIG_SYS_DDR_RCW_1           0x00000000
 #define CONFIG_SYS_DDR_RCW_2           0x00000000
@@ -110,7 +109,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
@@ -138,7 +136,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
@@ -166,7 +163,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
@@ -194,7 +190,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2

diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index 8ac3d5fbebf4779f9c672c536bbe89cc2ccd00da..0691ca455af472572d6736003c3f5cb549da50b3 100644 (file)
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -74,7 +74,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
        out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
        out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
-       out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl);
        out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
        out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 1689d680bdf6442bd715f808e6e2b2120bca6f51..5e63c5df3ad410acdc87df3e7d1e5894ef3271a2 100644 (file)
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1066,28 +1066,6 @@ static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
        ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
 }
 
-/* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */
-static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr)
-{
-       /* Termination value during pre-drive conditioning */
-       unsigned int tvpd = 0;
-       unsigned int pd_en = 0;         /* Pre-Drive Conditioning Enable */
-       unsigned int pdar = 0;          /* Pre-Drive After Read */
-       unsigned int pdaw = 0;          /* Pre-Drive After Write */
-       unsigned int pd_on = 0;         /* Pre-Drive Conditioning On */
-       unsigned int pd_off = 0;        /* Pre-Drive Conditioning Off */
-
-       ddr->ddr_pd_cntl = (0
-                           | ((pd_en & 0x1) << 31)
-                           | ((tvpd & 0x7) << 28)
-                           | ((pdar & 0x7F) << 20)
-                           | ((pdaw & 0x7F) << 12)
-                           | ((pd_on & 0x1F) << 6)
-                           | ((pd_off & 0x1F) << 0)
-                           );
-}
-
-
 /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
 static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
 {
@@ -1355,7 +1333,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        set_ddr_zq_cntl(ddr, zq_en);
        set_ddr_wrlvl_cntl(ddr, wrlvl_en);
 
-       set_ddr_pd_cntl(ddr);
        set_ddr_sr_cntr(ddr, sr_it);
 
        set_ddr_sdram_rcw_1(ddr);

diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index c2e5aeebcbfa70b15ee9c1f9dec2535b0ba11059..69b857b41cd1eb31f65e9b133d50a250927848f8 100644 (file)
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -110,7 +110,6 @@ typedef struct fsl_ddr_cfg_regs_s {
        unsigned int timing_cfg_5;
        unsigned int ddr_zq_cntl;
        unsigned int ddr_wrlvl_cntl;
-       unsigned int ddr_pd_cntl;
        unsigned int ddr_sr_cntr;
        unsigned int ddr_sdram_rcw_1;
        unsigned int ddr_sdram_rcw_2;

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 375d80444f5e8047ac8bfe173c1dba9aba6ad0d8..e7d412dba234872df60cf7347d2d3c2904b401b9 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -132,7 +132,7 @@ typedef struct ccsr_ddr {
        char    reg8_1a[8];
        uint    ddr_zq_cntl;            /* 0x2170 - DDR ZQ calibration control*/
        uint    ddr_wrlvl_cntl;         /* 0x2174 - DDR write leveling control*/
-       uint    ddr_pd_cntl;            /* 0x2178 - DDR pre-drive conditioning control*/
+       char    reg8_1aa[4];
        uint    ddr_sr_cntr;            /* 0x217C - DDR self refresh counter */
        uint    ddr_sdram_rcw_1;        /* 0x2180 - DDR Register Control Words 1 */
        uint    ddr_sdram_rcw_2;        /* 0x2184 - DDR Register Control Words 2 */