at91: 9x5: change SMC config timing that both works for PMECC & non-PMECC.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Tested-by: voice.shen@atmel.com
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 88b3478aaf45ef95a7fdd4ec35c6e20febd1d969..ae408bc9db1024407c9e9510029026d7414316a0 100644 (file)
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -65,13 +65,13 @@ static void at91sam9x5ek_nand_hw_init(void)
        writel(csa, &matrix->ebicsa);
 
        /* Configure SMC CS3 for NAND/SmartMedia */
-       writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
-               AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
                &smc->cs[3].setup);
-       writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
-               AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+               AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
                &smc->cs[3].pulse);
-       writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
                &smc->cs[3].cycle);
        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
                AT91_SMC_MODE_EXNW_DISABLE |
@@ -80,7 +80,7 @@ static void at91sam9x5ek_nand_hw_init(void)
 #else /* CONFIG_SYS_NAND_DBW_8 */
                AT91_SMC_MODE_DBW_8 |
 #endif
-               AT91_SMC_MODE_TDF_CYCLE(3),
+               AT91_SMC_MODE_TDF_CYCLE(1),
                &smc->cs[3].mode);
 
        writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);