powerpc/85xx: Add PBL boot from SPI flash support on P4080DS

PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.

Signed-off-by: Chunhe Lan <b25806@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 5642cd7b051c94682306f6bf7faeda71a09aa13e..6f256cf7a7b0493b1bc0ad64d24dbabc105f8b68 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -145,6 +145,22 @@ static void enable_cpc(void)
        for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
                u32 cpccfg0 = in_be32(&cpc->cpccfg0);
                size += CPC_CFG0_SZ_K(cpccfg0);
+#ifdef CONFIG_RAMBOOT_PBL
+               if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
+                       /* find and disable LAW of SRAM */
+                       struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
+
+                       if (law.index == -1) {
+                               printf("\nFatal error happened\n");
+                               return;
+                       }
+                       disable_law(law.index);
+
+                       clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
+                       out_be32(&cpc->cpccsr0, 0);
+                       out_be32(&cpc->cpcsrcr0, 0);
+               }
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
                setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
@@ -168,6 +184,9 @@ void invalidate_cpc(void)
        cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
        for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+               /* skip CPC when it used as all SRAM */
+               if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
+                       continue;
                /* Flash invalidate the CPC and clear all the locks */
                out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
                while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))

diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index 1ae0416248c7f8d0311108198803ad8d9be693bc..fe77e798a8c311ff8deb20ff91316b2502e0fbfd 100644 (file)
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -51,9 +51,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
        /* TLB 1 */
        /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+       /*
+        * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+        * SRAM is at 0xfff00000, it covered the 0xfffff000.
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 0, BOOKE_PAGESZ_1M, 1),
+#else
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
 
        /* *I*G* - CCSRBAR */
        SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,

diff --git a/boards.cfg b/boards.cfg
index d25f3f2392786e6590317a6ad0b589c4e435b1bb..c9c12785faef9cad564836ff26aa2cab519be672 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -542,6 +542,7 @@ P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SPIFLASH
 P4080DS                      powerpc     mpc85xx     corenet_ds          freescale
+P4080DS_RAMBOOT_PBL          powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF80000
 mpq101                       powerpc     mpc85xx     mpq101              mercury        -           mpq101
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 6f01211e7e8d12c9c11c6e1cf60760fdb2ebf041..4e2b3fb983d53ce35106bb9d1f993c33594f8174 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -28,6 +28,11 @@
 
 #include "../board/freescale/common/ics307_clk.h"
 
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE       CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500                    /* BOOKE e500 family */
@@ -63,12 +68,17 @@
 
 #define CONFIG_ENV_OVERWRITE
 
+#if defined(CONFIG_RAMBOOT_PBL)
+       #define CONFIG_SYS_NO_FLASH     /* Store ENV in memory only */
+#endif
+
 #ifdef CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_NOWHERE
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #endif
 
 #define CONFIG_SYS_CLK_FREQ    get_board_sys_clk() /* sysclk for MPC85xx */
@@ -99,6 +109,18 @@
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_PANIC_HANG      /* do not reset board on panic */
 
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR                CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS   (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS   CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE             (1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
@@ -192,6 +214,10 @@
 
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE    /* start of monitor */
 
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
@@ -439,7 +465,6 @@
 /*
  * Environment
  */
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE                0x2000
 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */