clk: zynqmp: Add gem rx and tsu clocks to return register

Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 53327cf9adc921a30eb5b8651a7ba1a1ffb8b25c..1cfe0e25b1052bae2644f0aaf75d177d9c708fb0 100644 (file)
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -270,17 +270,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
        case usb3_dual_ref:
                return CRL_APB_USB3_DUAL_REF_CTRL;
        case gem_tsu_ref:
+       case gem_tsu:
                return CRL_APB_GEM_TSU_REF_CTRL;
        case gem0_tx:
+       case gem0_rx:
        case gem0_ref:
                return CRL_APB_GEM0_REF_CTRL;
        case gem1_tx:
+       case gem1_rx:
        case gem1_ref:
                return CRL_APB_GEM1_REF_CTRL;
        case gem2_tx:
+       case gem2_rx:
        case gem2_ref:
                return CRL_APB_GEM2_REF_CTRL;
        case gem3_tx:
+       case gem3_rx:
        case gem3_ref:
                return CRL_APB_GEM3_REF_CTRL;
        case usb0_bus_ref: