armv8: Add workaround for USB erratum A-009798

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 64eadfd25ae1ca243bf9e7c3541d4038b7e21571..e77d8866c8d64ac2ccec7c5772e032c947bf49fa 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -19,6 +19,7 @@ config ARCH_LS1043A
        select SYS_FSL_ERRATUM_A009008
        select SYS_FSL_ERRATUM_A009660
        select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009798
        select SYS_FSL_ERRATUM_A009929
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
@@ -41,6 +42,7 @@ config ARCH_LS1046A
        select SYS_FSL_ERRATUM_A008511
        select SYS_FSL_ERRATUM_A008850
        select SYS_FSL_ERRATUM_A009008
+       select SYS_FSL_ERRATUM_A009798
        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009803
        select SYS_FSL_ERRATUM_A009942
@@ -105,6 +107,7 @@ config ARCH_LS2080A
        select SYS_FSL_ERRATUM_A009008
        select SYS_FSL_ERRATUM_A009635
        select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009798
        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009803
        select SYS_FSL_ERRATUM_A009942
@@ -254,6 +257,9 @@ endmenu
 config SYS_FSL_ERRATUM_A009008
        bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+       bool "Workaround for USB PHY erratum A009798"
+
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b9e3a2075acca2261198bd423139c10cdd56bfea..d9d6e4fd962365420d4a3bb89ef9e2e629e47077 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -65,6 +65,7 @@ static void erratum_a009008(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
        u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
        set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
        set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
@@ -75,6 +76,27 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
+{
+       scfg_clrbits32(scfg + offset / 4,
+                       SCFG_USB_SQRXTUNE_MASK << 23);
+}
+
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+       set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
+       set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
+       set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
+#elif defined(CONFIG_ARCH_LS2080A)
+       set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -222,6 +244,7 @@ void fsl_lsch3_early_init_f(void)
        erratum_a008514();
        erratum_a008336();
        erratum_a009008();
+       erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
        /* In case of Secure Boot, the IBR configures the SMMU
        * to allow only Secure transactions.
@@ -501,6 +524,7 @@ void fsl_lsch2_early_init_f(void)
        erratum_a009660();
        erratum_a010539();
        erratum_a009008();
+       erratum_a009798();
 }
 #endif
 

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 4e77102d067188a2721c95a2f043a251d67e9f25..17a4c086f0f400d5d64157630fb45eb65a451c05 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -342,6 +342,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2           0x07C
 #define SCFG_USB3PRM1CR_USB3           0x088
 #define SCFG_USB_TXVREFTUNE                    0x9
+#define SCFG_USB_SQRXTUNE_MASK         0x7
 
 #define SCFG_SNPCNFGCR_SECRDSNP                0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP                0x40000000

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 6e4d243b07526f71387d7af3aedc6a71e9ea2dfd..3c91e69bd9011d218bf729d0ccdfb2d03f43a15a 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -134,6 +134,7 @@
 #define SCFG_USB3PRM1CR                        0x000
 #define SCFG_USB3PRM1CR_INIT           0x27672b2a
 #define SCFG_USB_TXVREFTUNE            0x9
+#define SCFG_USB_SQRXTUNE_MASK 0x7
 #define SCFG_QSPICLKCTLR       0x10
 
 #define TP_ITYP_AV             0x00000001      /* Initiator available */