/* Wait for end of hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
/* avoid shutdown by watchdog */
- WATCHDOG_RESET();
+ schedule();
mdelay(10);
/* timeout for not getting stuck in an endless loop */
scl = gpio_get_value(p->scl.gp);
if ((sda & scl) == 1)
break;
- WATCHDOG_RESET();
+ schedule();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
ret = -EBUSY;
/* enable console uart printing */
preloader_console_init();
- WATCHDOG_RESET();
+ schedule();
arch_early_init_r();
*/
set_regular_boot(true);
- WATCHDOG_RESET();
+ schedule();
reset_cpu();
}
/* reconfigure and enable the watchdog */
hw_watchdog_init();
- WATCHDOG_RESET();
+ schedule();
#endif /* CONFIG_HW_WATCHDOG */
config_dedicated_pins(gd->fdt_blob);
- WATCHDOG_RESET();
+ schedule();
}
/* board specific function prior loading SSBL / U-Boot proper */
err = ops->getc(down_serial_dev);
if (err == -EAGAIN) {
ctrlc();
- WATCHDOG_RESET();
+ schedule();
}
} while ((err == -EAGAIN) && (!had_ctrlc()));
*count -= 1;
} else if (err == -EAGAIN) {
ctrlc();
- WATCHDOG_RESET();
+ schedule();
if (get_timer(start) > TIMEOUT_SERIAL_BUFFER) {
err = -ETIMEDOUT;
break;
stm32prog_serial_result(ACK_BYTE);
cmd_func[counter](data);
}
- WATCHDOG_RESET();
+ schedule();
}
/* clean device */
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
- WATCHDOG_RESET ();
+ schedule();
}
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
return;
out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
#endif
- WATCHDOG_RESET();
+ schedule();
/* SIUMCR - contains debug pin configuration (11-6) */
setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
* r9: 0
*/
debug(" Booting using OF flat tree...\n");
- WATCHDOG_RESET ();
+ schedule();
(*kernel) ((struct bd_info *)of_flat_tree, 0, 0, EPAPR_MAGIC,
env_get_bootm_mapsize(), 0, 0);
/* does not return */
struct bd_info *kbd = images->kbd;
debug(" Booting using board info...\n");
- WATCHDOG_RESET ();
+ schedule();
(*kernel) (kbd, initrd_start, initrd_end,
cmd_start, cmd_end, 0, 0);
/* does not return */
* r9: 0
* TCR: WRC = 0, no watchdog timer reset will occur
*/
- WATCHDOG_RESET();
+ schedule();
((void (*)(void *, ulong, ulong, ulong,
ulong, ulong, ulong))images->ep)(images->ft_addr,
{
flushed += CONFIG_SYS_CACHELINE_SIZE;
if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
- WATCHDOG_RESET();
+ schedule();
flushed = 0;
}
return flushed;
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
- WATCHDOG_RESET ();
+ schedule();
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
#ifdef CONFIG_LED_STATUS
if (bytecount % len_40 == 0) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
+ schedule();
#endif
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc('.'); /* let them know we are alive */
}
if (bytecount % len_40 == 0) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
+ schedule();
#endif
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc('.'); /* let them know we are alive */
for (i = 0; i < 2 * nb_blink; i++) {
led_set_state(led, LEDST_TOGGLE);
mdelay(125);
- WATCHDOG_RESET();
+ schedule();
}
}
#endif
/* Initialize and reset WDT in SPL */
#ifdef CONFIG_SPL_WATCHDOG
hw_watchdog_init();
- WATCHDOG_RESET();
+ schedule();
#endif
/* load/boot image from boot device */
{
keybuf_head %= KEYBUF_SIZE;
while (!rx51_kp_tstc(dev))
- WATCHDOG_RESET();
+ schedule();
return keybuf[keybuf_head++];
}
for (i = 0; i < 2 * nb_blink; i++) {
led_set_state(led, LEDST_TOGGLE);
mdelay(125);
- WATCHDOG_RESET();
+ schedule();
}
led_set_state(led, LEDST_ON);
}
while (!tstc()) { /* while no incoming data */
if (retry_time >= 0 && get_ticks() > endtime)
return -ETIMEDOUT;
- WATCHDOG_RESET();
+ schedule();
}
return 0;
while (len > 0) {
size_t tail = (len > chunksz) ? chunksz : len;
- WATCHDOG_RESET();
+ schedule();
if (to > from) {
to -= tail;
from -= tail;
break;
if (ctrlc())
break;
- WATCHDOG_RESET();
+ schedule();
usb_gadget_handle_interrupts(controller_index);
}
/* reset watchdog from time to time */
if ((ngood % (64 << 10)) == 0)
- WATCHDOG_RESET();
+ schedule();
}
unmap_sysmem(buf1);
unmap_sysmem(buf2);
}
}
addr[test_offset] = pattern;
- WATCHDOG_RESET();
+ schedule();
/*
* Check for addr bits stuck low or shorted.
* Fill memory with a known pattern.
*/
for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
- WATCHDOG_RESET();
+ schedule();
addr[offset] = pattern;
}
* Check each location and invert it for the second pass.
*/
for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
- WATCHDOG_RESET();
+ schedule();
temp = addr[offset];
if (temp != pattern) {
printf("\nFAILURE (read/write) @ 0x%.8lx:"
* Check each location for the inverted pattern and zero it.
*/
for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
- WATCHDOG_RESET();
+ schedule();
anti_pattern = ~pattern;
temp = addr[offset];
if (temp != anti_pattern) {
for (k = 0; k < max; k++) {
q = 0x00000001L << k;
for (j = 0; j < 8; j++) {
- WATCHDOG_RESET();
+ schedule();
q = ~q;
p1 = (volatile unsigned long *)bufa;
p2 = (volatile unsigned long *)bufb;
pattern, "");
for (addr = buf, val = pattern; addr < end; addr++) {
- WATCHDOG_RESET();
+ schedule();
*addr = val;
val += incr;
}
puts("Reading...");
for (addr = buf, val = pattern; addr < end; addr++) {
- WATCHDOG_RESET();
+ schedule();
readback = *addr;
if (readback != val) {
ulong offset = addr - buf;
goto cleanup_register;
}
- WATCHDOG_RESET();
+ schedule();
}
cleanup_register:
while (l > 0) {
tail = (l > CHUNKSZ) ? CHUNKSZ : l;
- WATCHDOG_RESET();
+ schedule();
memmove(to, from, tail);
to += tail;
from += tail;
hw_watchdog_init();
puts(" Watchdog enabled\n");
# endif
- WATCHDOG_RESET();
+ schedule();
return 0;
}
int init_func_watchdog_reset(void)
{
- WATCHDOG_RESET();
+ schedule();
return 0;
}
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
- * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
+ * NOTE: Maybe we should add some schedule()? XXX
*/
if (env_get_yesno("flashchecksum") == 1) {
const uchar *flash_base = (const uchar *)CONFIG_SYS_FLASH_BASE;
while (!tstc()) { /* while no incoming data */
if (get_ticks() >= etime)
return -2; /* timed out */
- WATCHDOG_RESET();
+ schedule();
}
first = 0;
}
for (;;) {
if (bootretry_tstc_timeout())
return -2; /* timed out */
- WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+ schedule(); /* Trigger watchdog, if needed */
c = getchar();
* Effectively poll for input wherever it may be available.
*/
for (;;) {
- WATCHDOG_RESET();
+ schedule();
if (CONFIG_IS_ENABLED(CONSOLE_MUX)) {
/*
* Upper layer may have already called tstc() so
if (dfu_reinit_needed)
goto exit;
- WATCHDOG_RESET();
+ schedule();
usb_gadget_handle_interrupts(usbctrl_index);
}
exit:
BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS);
if (bpix < 12) {
- WATCHDOG_RESET();
+ schedule();
lcd_logo_set_cmap();
- WATCHDOG_RESET();
+ schedule();
for (i = 0; i < BMP_LOGO_HEIGHT; ++i) {
memcpy(fb, bmap, BMP_LOGO_WIDTH);
}
}
- WATCHDOG_RESET();
+ schedule();
lcd_sync();
}
#else
byte_width = width * 2;
for (i = 0; i < height; ++i) {
- WATCHDOG_RESET();
+ schedule();
for (j = 0; j < width; j++) {
if (bpix != 16) {
fb_put_byte(&fb, &bmap);
#if defined(CONFIG_BMP_16BPP)
case 16:
for (i = 0; i < height; ++i) {
- WATCHDOG_RESET();
+ schedule();
for (j = 0; j < width; j++)
fb_put_word(&fb, &bmap);
printf("Hit any key to stop autoboot: %d ", menu->delay);
for (i = 0; i < 100; ++i) {
if (!tstc()) {
- WATCHDOG_RESET();
+ schedule();
mdelay(10);
continue;
}
if (tstc()) {
c = getchar();
} else {
- WATCHDOG_RESET();
+ schedule();
mdelay(10);
if (tstc())
c = getchar();
}
} else {
while (!tstc()) {
- WATCHDOG_RESET();
+ schedule();
mdelay(10);
}
c = getchar();
data = usb_kbd_dev->privptr;
while (data->usb_in_pointer == data->usb_out_pointer) {
- WATCHDOG_RESET();
+ schedule();
usb_kbd_poll_for_event(usb_kbd_dev);
}
{
ulong now = get_timer(0);
- WATCHDOG_RESET();
+ schedule();
while (!tstc ())
{
if (get_timer(now) > xyzModem_CHAR_TIMEOUT)
/* the reset signal shall be asserted for et least 25 us */
udelay(25);
- WATCHDOG_RESET();
+ schedule();
/* de-assert RESET signal */
ide_set_reset(0);
unsigned char c;
int i, bus;
- WATCHDOG_RESET();
+ schedule();
/* ATAPI Drives seems to need a proper IDE Reset */
ide_reset();
puts("OK ");
ide_bus_ok[bus] = 1;
}
- WATCHDOG_RESET();
+ schedule();
}
putc('\n');
}
#endif
}
- WATCHDOG_RESET();
+ schedule();
#ifdef CONFIG_BLK
struct udevice *dev;
return rc;
cur += chunk;
- WATCHDOG_RESET();
+ schedule();
}
} else {
rc = aspeed_hace_update(dev, ctx, ibuf, ilen);
return rc;
cur += chunk;
- WATCHDOG_RESET();
+ schedule();
}
} else {
rc = sw_hash_update(dev, ctx, ibuf, ilen);
int ddr_calibration_sequence(void)
{
- WATCHDOG_RESET();
+ schedule();
/* Check to see if SDRAM cal was success */
if (sdram_startup()) {
puts("DDRCAL: Success\n");
- WATCHDOG_RESET();
+ schedule();
/* initialize the MMR register */
sdram_mmr_init();
DDR4_CRCPARSTAT_CMD_IN_ERR_WINDOW;
udelay(1);
- WATCHDOG_RESET();
+ schedule();
}
return 0;
}
udelay(1);
- WATCHDOG_RESET();
+ schedule();
/* Polling until SDRAM entered normal operating mode */
value = readl(umctl2_base + DDR4_STAT_OFFSET) &
sdram_clear_mem(start_addr, size_init);
size -= size_init;
start_addr += size_init;
- WATCHDOG_RESET();
+ schedule();
}
bank++;
puts(".");
udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
- WATCHDOG_RESET();
+ schedule();
}
return -ETIMEDOUT;
udelay(20000);
}
- WATCHDOG_RESET();
+ schedule();
}
return 0;
puts(".");
udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
- WATCHDOG_RESET();
+ schedule();
}
return -ETIMEDOUT;
if (resp_err && !xfer_count)
return resp_err;
}
- WATCHDOG_RESET();
+ schedule();
}
return 0;
printf("nstatus == 0 while waiting for condone\n");
return -EPERM;
}
- WATCHDOG_RESET();
+ schedule();
}
if (i == FPGA_TIMEOUT_CNT)
rbf->section = unknown;
break;
- WATCHDOG_RESET();
+ schedule();
}
}
break;
}
}
- WATCHDOG_RESET();
+ schedule();
}
if (!fpga_node_name) {
total_sizeof_image += buffer_sizebytes_ori;
- WATCHDOG_RESET();
+ schedule();
}
wait_for_fifo_empty();
}
if ((sr & (state >> 8)) == (unsigned char)state)
return sr;
- WATCHDOG_RESET();
+ schedule();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
break;
sda = dm_gpio_get_value(sda_gpio);
if ((sda & scl) == 1)
break;
- WATCHDOG_RESET();
+ schedule();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
ret = -EBUSY;
start = get_timer(0);
do {
rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
- WATCHDOG_RESET();
+ schedule();
} while (get_timer(start) < 100 &&
(rsp_sts.s.dma_val || rsp_sts.s.dma_pend));
} while (retries-- >= 0 && rsp_sts.s.dma_pend);
} else if (!rsp_sts.s.dma_val && emm_dma_int.s.done) {
break;
}
- WATCHDOG_RESET();
+ schedule();
timed_out = (get_timer(start_time) > timeout);
} while (!timed_out);
}
return blkcnt - count;
}
- WATCHDOG_RESET();
+ schedule();
} while (--count);
}
#ifdef DEBUG
} else if (cmd.response[0] & R1_READY_FOR_DATA) {
return 0;
}
- WATCHDOG_RESET();
+ schedule();
} while (get_timer(start) < timeout);
if (not_ready)
read_csr(mmc, MIO_EMM_DMA()));
return blkcnt - count;
}
- WATCHDOG_RESET();
+ schedule();
} while (--count);
}
start = get_timer(0);
do {
rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
- WATCHDOG_RESET();
+ schedule();
} while (!rsp_sts.s.cmd_done && !rsp_sts.s.rsp_timeout &&
(get_timer(start) < timeout + 10));
octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
for (i = 0; i < blocksize / 4; i++)
*p++ = sh_mmcif_read(&host->regs->ce_data);
- WATCHDOG_RESET();
+ schedule();
}
return 0;
}
for (i = 0; i < blocksize / 4; i++)
sh_mmcif_write(*p++, &host->regs->ce_data);
- WATCHDOG_RESET();
+ schedule();
}
return 0;
}
{
int ret;
- WATCHDOG_RESET();
+ schedule();
switch (cmd->cmdidx) {
case MMC_CMD_APP_CMD:
u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
int ret, retry = 3;
- WATCHDOG_RESET();
+ schedule();
retry_cmd:
ctx.data_length = 0;
reset_timer();
#endif
start = get_timer(0);
- WATCHDOG_RESET();
+ schedule();
while (flash_is_busy(info, sector)) {
if (get_timer(start) > tout) {
printf("Flash %s timeout at address %lx data %lx\n",
reset_timer();
#endif
start = get_timer(0);
- WATCHDOG_RESET();
+ schedule();
while (1) {
switch (info->portwidth) {
case FLASH_CFI_8BIT:
nanddev_offs_to_pos(nand, einfo->addr, &pos);
nanddev_offs_to_pos(nand, einfo->addr + einfo->len - 1, &last);
while (nanddev_pos_cmp(&pos, &last) <= 0) {
- WATCHDOG_RESET();
+ schedule();
ret = nanddev_erase(nand, &pos);
if (ret) {
einfo->fail_addr = nanddev_pos_to_offs(nand, &pos);
while (--timeout) {
if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
break;
- WATCHDOG_RESET();
+ schedule();
udelay(1);
}
while (--timeout) {
if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
break;
- WATCHDOG_RESET();
+ schedule();
udelay(1);
}
while (--timeout) {
if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
break;
- WATCHDOG_RESET();
+ schedule();
udelay(1);
}
if (status & NAND_STATUS_READY)
break;
- WATCHDOG_RESET();
+ schedule();
}
};
while (1) {
unsigned int ecc_failures = mtd->ecc_stats.failed;
- WATCHDOG_RESET();
+ schedule();
bytes = min(mtd->writesize - col, readlen);
aligned = (bytes == mtd->writesize);
page = realpage & chip->pagemask;
while (1) {
- WATCHDOG_RESET();
+ schedule();
if (ops->mode == MTD_OPS_RAW)
ret = chip->ecc.read_oob_raw(mtd, chip, page);
else
use_bufpoi = 0;
- WATCHDOG_RESET();
+ schedule();
/* Partial page write?, or need to use bounce buffer */
if (use_bufpoi) {
pr_debug("%s: using write bounce buffer for buf@%p\n",
instr->state = MTD_ERASING;
while (len) {
- WATCHDOG_RESET();
+ schedule();
/* Check if we have a bad block, we do not erase bad blocks! */
if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
erased_length < erase_length;
erase.addr += mtd->erasesize) {
- WATCHDOG_RESET();
+ schedule();
if (opts->lim && (erase.addr >= (opts->offset + opts->lim))) {
puts("Size of erase exceeds limit\n");
size_t block_offset = offset & (mtd->erasesize - 1);
size_t write_size, truncated_write_size;
- WATCHDOG_RESET();
+ schedule();
if (nand_block_isbad(mtd, block_start)) {
printf("Skip bad block 0x%08llx\n", block_start);
size_t block_offset = offset & (mtd->erasesize - 1);
size_t read_length;
- WATCHDOG_RESET();
+ schedule();
if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) {
printf("Skipping bad block 0x%08llx\n",
#endif
nanddev_io_for_each_page(nand, from, ops, &iter) {
- WATCHDOG_RESET();
+ schedule();
ret = spinand_select_target(spinand, iter.req.pos.target);
if (ret)
break;
#endif
nanddev_io_for_each_page(nand, to, ops, &iter) {
- WATCHDOG_RESET();
+ schedule();
ret = spinand_select_target(spinand, iter.req.pos.target);
if (ret)
break;
u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
u32 time_start = get_timer(0);
do {
- WATCHDOG_RESET();
+ schedule();
if (get_timer(time_start) > timeo)
return -EIO;
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
u32 time_start = get_timer(0);
do {
- WATCHDOG_RESET();
+ schedule();
if (get_timer(time_start) > timeo)
return ONENAND_BBT_READ_FATAL_ERROR;
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
addr_known = true;
while (len) {
- WATCHDOG_RESET();
+ schedule();
if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) {
addr_known = false;
ret = -EINTR;
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
- WATCHDOG_RESET();
+ schedule();
/*
* If page_size is a power of two, the offset can be quickly
__iowmb();
result = lmt_submit((u64)(nix->nix_base +
NIXX_LF_OP_SENDX(0)));
- WATCHDOG_RESET();
+ schedule();
} while (result == 0);
return 0;
start = get_timer(0);
while ((res->s.compcode == NPA_AQ_COMP_E_NOTDONE) &&
(get_timer(start) < 1000))
- WATCHDOG_RESET();
+ schedule();
if (res->s.compcode != NPA_AQ_COMP_E_GOOD) {
printf("%s: Error: result 0x%x not good\n",
__func__, res->s.compcode);
start = get_timer(0);
while ((res->s.compcode == NPA_AQ_COMP_E_NOTDONE) &&
(get_timer(start) < 1000))
- WATCHDOG_RESET();
+ schedule();
if (res->s.compcode != NPA_AQ_COMP_E_GOOD) {
printf("%s: Error: result 0x%x not good\n",
do {
lf_rst.u = npa_af_reg_read(npa_af, NPA_AF_LF_RST());
- WATCHDOG_RESET();
+ schedule();
} while (lf_rst.s.exec);
/* Set Aura size and enable caching of contexts */
start = get_timer(0);
while ((res->s.compcode == NPA_AQ_COMP_E_NOTDONE) &&
(get_timer(start) < 1000))
- WATCHDOG_RESET();
+ schedule();
if (res->s.compcode != NPA_AQ_COMP_E_GOOD) {
printf("%s: Error: result 0x%x not good for lf %d\n"
start = get_timer(0);
while ((res->s.compcode == NPA_AQ_COMP_E_NOTDONE) &&
(get_timer(start) < 1000))
- WATCHDOG_RESET();
+ schedule();
if (res->s.compcode != NPA_AQ_COMP_E_GOOD) {
printf("%s: Error: result 0x%x not good for lf %d\n"
do {
lf_rst.u = npa_af_reg_read(npa, NPA_AF_LF_RST());
- WATCHDOG_RESET();
+ schedule();
} while (lf_rst.s.exec);
return 0;
/* Wait for reset to complete */
do {
blk_rst.u = npa_af_reg_read(npa_af, NPA_AF_BLK_RST());
- WATCHDOG_RESET();
+ schedule();
} while (blk_rst.s.busy);
/* Set little Endian */
/* Wait for reset to complete */
do {
blk_rst.u = npa_af_reg_read(npa_af, NPA_AF_BLK_RST());
- WATCHDOG_RESET();
+ schedule();
} while (blk_rst.s.busy);
rvu_aq_free(&npa_af->aq);
start = get_timer(0);
/* Wait for completion */
do {
- WATCHDOG_RESET();
+ schedule();
dsb();
} while (result->s.compcode == 0 && get_timer(start) < 2);
do {
lf_rst.u = nix_af_reg_read(nix_af, NIXX_AF_LF_RST());
- WATCHDOG_RESET();
+ schedule();
} while (lf_rst.s.exec);
/* Config NIX RQ HW context and base*/
do {
sw_sync.u = nix_af_reg_read(nix_af, NIXX_AF_RX_SW_SYNC());
- WATCHDOG_RESET();
+ schedule();
} while (sw_sync.s.ena);
for (index = 0; index < rq_count; index++) {
do {
lf_rst.u = nix_af_reg_read(nix_af, NIXX_AF_LF_RST());
- WATCHDOG_RESET();
+ schedule();
} while (lf_rst.s.exec);
return 0;
/* Wait for reset to complete */
do {
blk_rst.u = npc_af_reg_read(nix_af, NPC_AF_BLK_RST());
- WATCHDOG_RESET();
+ schedule();
} while (blk_rst.s.busy);
debug("%s: npc af reset --\n", __func__);
/* Wait for reset to complete */
do {
blk_rst.u = nix_af_reg_read(nix_af, NIXX_AF_BLK_RST());
- WATCHDOG_RESET();
+ schedule();
} while (blk_rst.s.busy);
/* Put in LE mode */
/* Wait for calibration to complete */
do {
af_status.u = nix_af_reg_read(nix_af, NIXX_AF_STATUS());
- WATCHDOG_RESET();
+ schedule();
} while (af_status.s.calibrate_done == 0);
af_cfg.u = nix_af_reg_read(nix_af, NIXX_AF_CFG());
/* Wait for reset to complete */
do {
blk_rst.u = nix_af_reg_read(nix_af, NIXX_AF_BLK_RST());
- WATCHDOG_RESET();
+ schedule();
} while (blk_rst.s.busy);
rvu_aq_free(&nix_af->aq);
return 1;
}
printf("loop #%d\n", *loop);
- WATCHDOG_RESET();
+ schedule();
return 0;
}
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
- WATCHDOG_RESET();
+ schedule();
return readl(&usart->rhr);
}
* in puts().
*/
if (c == '\n')
- WATCHDOG_RESET();
+ schedule();
}
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
extern void usbtty_poll(void);
usbtty_poll();
#endif
- WATCHDOG_RESET();
+ schedule();
}
return serial_in(&com_port->rbr);
}
* in puts().
*/
if (ch == '\n')
- WATCHDOG_RESET();
+ schedule();
return 0;
}
do {
err = ops->getc(dev);
if (err == -EAGAIN)
- WATCHDOG_RESET();
+ schedule();
} while (err == -EAGAIN);
return err >= 0 ? err : 0;
lsr = readl(®s->lsr);
if (input) {
- WATCHDOG_RESET();
+ schedule();
return (lsr & BCM283X_MU_LSR_RX_READY) ? 1 : 0;
} else {
return (lsr & BCM283X_MU_LSR_TX_IDLE) ? 0 : 1;
{
struct lpuart_fsl *base = plat->reg;
while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
- WATCHDOG_RESET();
+ schedule();
barrier();
struct lpuart_fsl *base = plat->reg;
while (!(__raw_readb(&base->us1) & US1_TDRE))
- WATCHDOG_RESET();
+ schedule();
__raw_writeb(c, &base->ud);
}
lpuart_read32(plat->flags, &base->stat, &stat);
while ((stat & STAT_RDRF) == 0) {
lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
- WATCHDOG_RESET();
+ schedule();
lpuart_read32(plat->flags, &base->stat, &stat);
}
if ((stat & STAT_TDRE))
break;
- WATCHDOG_RESET();
+ schedule();
}
lpuart_write32(plat->flags, &base->data, c);
setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
- WATCHDOG_RESET();
+ schedule();
return 0;
}
/* Wait for character to show up. */
while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
- WATCHDOG_RESET();
+ schedule();
/* the characters are read one by one,
* use the rxindex to know the next char to deliver
writel(ch, &plat->regs->thr);
if (ch == '\n')
- WATCHDOG_RESET();
+ schedule();
return 0;
}
writel(ch, &priv->regs->thr);
if (ch == '\n')
- WATCHDOG_RESET();
+ schedule();
return 0;
}
do { \
err = _mtk_serial_getc(&mtk_hsuart##port); \
if (err == -EAGAIN) \
- WATCHDOG_RESET(); \
+ schedule(); \
} while (err == -EAGAIN); \
return err >= 0 ? err : 0; \
} \
static int mxc_serial_getc(void)
{
while (readl(&mxc_base->ts) & UTS_RXEMPTY)
- WATCHDOG_RESET();
+ schedule();
return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
}
/* wait for transmitter to be ready */
while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
- WATCHDOG_RESET();
+ schedule();
}
/* Test whether a character is in the RX buffer */
struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(readl(&base->ts) & UTS_TXEMPTY))
- WATCHDOG_RESET();
+ schedule();
writel(ch, &base->txd);
}
}
while (!octeon_bootcmd_pending(dev, true)) {
- WATCHDOG_RESET();
+ schedule();
/*
* ToDo:
* The original code calls octeon_board_poll() here. We may
cons_ptr->input_write_index,
cons_ptr->input_read_index))) {
mdelay(10);
- WATCHDOG_RESET();
+ schedule();
}
}
if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
goto done;
- WATCHDOG_RESET();
+ schedule();
mdelay(10); /* Delay if we are spinning */
} else {
bytes_written = -1;
static int pl01x_tstc(struct pl01x_regs *regs)
{
- WATCHDOG_RESET();
+ schedule();
return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
}
int ch = pl01x_getc(base_regs);
if (ch == -EAGAIN) {
- WATCHDOG_RESET();
+ schedule();
continue;
}
* crap in console
*/
while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
- WATCHDOG_RESET();
+ schedule();
while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
- WATCHDOG_RESET();
+ schedule();
pl01x_serial_init_baud(gd->baudrate);
}
(struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
while (_sifive_serial_putc(regs, ch) == -EAGAIN)
- WATCHDOG_RESET();
+ schedule();
}
DEBUG_UART_FUNCS
struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
- WATCHDOG_RESET();
+ schedule();
}
DEBUG_UART_FUNCS
int addr_sh;
int ret;
- WATCHDOG_RESET();
+ schedule();
ret = mtk_snfi_mac_reset(priv);
if (ret)
do {
mpi_sts = readq(base + MPI_STS);
- WATCHDOG_RESET();
+ schedule();
} while (mpi_sts & MPI_STS_BUSY);
debug("%s(%s)\n", __func__, dev->name);
static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
{
*val = readb(addr);
- WATCHDOG_RESET();
+ schedule();
}
static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
if (CONFIG_SYS_WATCHDOG_FREQ && (priv->timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
- WATCHDOG_RESET();
+ schedule();
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
#ifdef CONFIG_LED_STATUS
ulong end = get_ticks() + ticks;
while (end > get_ticks())
- WATCHDOG_RESET();
+ schedule();
}
static u64 mpc83xx_timer_get_count(struct udevice *dev)
}
udelay(1);
- WATCHDOG_RESET();
+ schedule();
}
debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg,
}
udelay(1);
- WATCHDOG_RESET();
+ schedule();
}
debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg,
/* Wait for a character to arrive. */
while (!acm_stdio_tstc(dev))
- WATCHDOG_RESET();
+ schedule();
buf_pop(&f_acm->rx_buf, &c, 1);
if (ctrlc())
return -ECANCELED;
- WATCHDOG_RESET();
+ schedule();
}
return 0;
return 1;
}
- WATCHDOG_RESET();
+ schedule();
usb_gadget_handle_interrupts(controller_index);
}
if (flag == SDP_EXIT)
return 0;
- WATCHDOG_RESET();
+ schedule();
usb_gadget_handle_interrupts(controller_index);
#ifdef CONFIG_SPL_BUILD
token = hc32_to_cpu(vtd->qt_token);
if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
break;
- WATCHDOG_RESET();
+ schedule();
} while (get_timer(ts) < timeout);
qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token);
int usb_gadget_handle_interrupts(int index)
{
- WATCHDOG_RESET();
+ schedule();
if (!gadget || !gadget->isr)
return -EINVAL;
byte_width = width;
for (i = 0; i < height; ++i) {
- WATCHDOG_RESET();
+ schedule();
for (j = 0; j < width; j++) {
write_pix8(fb, bpix, eformat, palette, bmap);
bmap++;
case 16:
if (IS_ENABLED(CONFIG_BMP_16BPP)) {
for (i = 0; i < height; ++i) {
- WATCHDOG_RESET();
+ schedule();
for (j = 0; j < width; j++) {
*fb++ = *bmap++;
*fb++ = *bmap++;
if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
struct env_entry e, *ep;
- WATCHDOG_RESET();
+ schedule();
e.key = name;
e.data = NULL;
*/
#include <common.h>
+#include <cyclic.h>
#include <malloc.h>
#include <watchdog.h>
#include <u-boot/zlib.h>
stream.avail_in = 0;
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- stream.outcb = (cb_func)watchdog_reset_func;
+ stream.outcb = (cb_func)cyclic_run;
#else
stream.outcb = Z_NULL;
#endif /* CONFIG_HW_WATCHDOG */
/* Set buf_size to maximum length */
buf_size = DEFAULT_EMPTY_SCAN_SIZE;
- WATCHDOG_RESET();
+ schedule();
#ifdef CONFIG_JFFS2_SUMMARY
buf_len = sizeof(*sm);
#define _LINUX_COMPAT_H_
#include <console.h>
+#include <cyclic.h>
#include <log.h>
#include <malloc.h>
#define try_to_freeze(...) 0
#define set_current_state(...) do { } while (0)
#define kthread_should_stop(...) 0
-#define schedule() do { } while (0)
#define setup_timer(timer, func, data) do {} while (0)
#define del_timer_sync(timer) do {} while (0)
} \
\
udelay(1); \
- WATCHDOG_RESET(); \
+ schedule(); \
} \
\
debug("%s: Timeout (reg=%p mask=%x wait_set=%i)\n", __func__, \
#endif /* CONFIG_WATCHDOG && !__ASSEMBLY__ */
#endif /* CONFIG_HW_WATCHDOG */
-#if !defined(__ASSEMBLY__)
-/* Currently only needed for fs/cramfs/uncompress.c */
-static inline void watchdog_reset_func(void)
-{
- WATCHDOG_RESET();
-}
-#endif
-
/*
* Prototypes from $(CPU)/cpu.c.
*/
while (True) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
+ schedule();
#endif
if (s->state == BZ_X_IDLE) return BZ_SEQUENCE_ERROR;
if (s->state == BZ_X_OUTPUT) {
while (True) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
+ schedule();
#endif
if (nextSym == EOB) break;
kk = MTFA_SIZE-1;
for (ii = 256 / MTFL_SIZE-1; ii >= 0; ii--) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
+ schedule();
#endif
for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
s->mtfa[kk] = s->mtfa[s->mtfbase[ii] + jj];
while (i != s->origPtr);
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
+ schedule();
#endif
s->tPos = s->origPtr;
s->nblock_used = 0;
} else {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
- WATCHDOG_RESET();
+ schedule();
#endif
/*-- compute the T^(-1) vector --*/
for (i = 0; i < nblock; i++) {
chunk = chunk_sz;
crc = crc32(crc, curr, chunk);
curr += chunk;
- WATCHDOG_RESET ();
+ schedule();
}
#else
crc = crc32(crc, buf, len);
efi_signal_event(evt);
}
efi_process_event_queue();
- WATCHDOG_RESET();
+ schedule();
}
/**
/* Give the payload some time to boot */
efi_set_watchdog(0);
- WATCHDOG_RESET();
+ schedule();
out:
if (IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL)) {
if (ret != EFI_SUCCESS)
puts("abort\n");
goto out;
}
- WATCHDOG_RESET();
+ schedule();
} while (s.avail_out == 0);
/* done when inflate() says it's done */
} while (r != Z_STREAM_END);
UInt32 range = p->range;
UInt32 code = p->code;
- WATCHDOG_RESET();
+ schedule();
do
{
state -= (state < 4) ? state : 3;
symbol = 1;
- WATCHDOG_RESET();
+ schedule();
do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);
}
state -= (state < 10) ? 3 : 6;
symbol = 1;
- WATCHDOG_RESET();
+ schedule();
do
{
UInt32 mask = 1;
unsigned i = 1;
- WATCHDOG_RESET();
+ schedule();
do
{
{
numDirectBits -= kNumAlignBits;
- WATCHDOG_RESET();
+ schedule();
do
{
const Byte *lim = dest + curLen;
dicPos += curLen;
- WATCHDOG_RESET();
+ schedule();
do
*(dest) = (Byte)*(dest + src);
else
{
- WATCHDOG_RESET();
+ schedule();
do
{
}
while (dicPos < limit && buf < bufLimit);
- WATCHDOG_RESET();
+ schedule();
NORMALIZE;
p->buf = buf;
/* Decompress */
outProcessed = min(outSizeFull, *uncompressedSize);
- WATCHDOG_RESET();
+ schedule();
res = LzmaDecode(
outStream, &outProcessed,
chunk = chunk_sz;
MD5Update(&context, curr, chunk);
curr += chunk;
- WATCHDOG_RESET ();
+ schedule();
}
#else
MD5Update(&context, input, len);
chunk = chunk_sz;
sha1_update (&ctx, curr, chunk);
curr += chunk;
- WATCHDOG_RESET ();
+ schedule();
}
#else
sha1_update (&ctx, input, ilen);
chunk = chunk_sz;
sha256_update(&ctx, curr, chunk);
curr += chunk;
- WATCHDOG_RESET();
+ schedule();
}
#else
sha256_update(&ctx, input, ilen);
chunk = chunk_sz;
sha384_update(&ctx, curr, chunk);
curr += chunk;
- WATCHDOG_RESET();
+ schedule();
}
#else
sha384_update(&ctx, input, ilen);
chunk = chunk_sz;
sha512_update(&ctx, curr, chunk);
curr += chunk;
- WATCHDOG_RESET();
+ schedule();
}
#else
sha512_update(&ctx, input, ilen);
ulong kv;
do {
- WATCHDOG_RESET();
+ schedule();
kv = usec > CONFIG_WD_PERIOD ? CONFIG_WD_PERIOD : usec;
__udelay(kv);
usec -= kv;
state->hold = 0;
state->bits = 0;
state->lencode = state->distcode = state->next = state->codes;
- WATCHDOG_RESET();
+ schedule();
Tracev((stderr, "inflate: reset\n"));
return Z_OK;
}
strm->adler = state->check = adler32(0L, Z_NULL, 0);
state->mode = TYPE;
case TYPE:
- WATCHDOG_RESET();
+ schedule();
if (flush == Z_BLOCK) goto inf_leave;
case TYPEDO:
if (state->last) {
Tracev((stderr, "inflate: codes ok\n"));
state->mode = LEN;
case LEN:
- WATCHDOG_RESET();
+ schedule();
if (have >= 6 && left >= 258) {
RESTORE();
inflate_fast(strm, out);
return Z_STREAM_ERROR;
state = (struct inflate_state FAR *)strm->state;
if (state->window != Z_NULL) {
- WATCHDOG_RESET();
+ schedule();
ZFREE(strm, state->window);
}
ZFREE(strm, strm->state);
* someone sets `net_state' to a state that terminates.
*/
for (;;) {
- WATCHDOG_RESET();
+ schedule();
if (arp_timeout_check() > 0)
time_start = get_timer(0);
for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
- WATCHDOG_RESET();
+ schedule();
ecc_clear(ddr);
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = val;
if (i % 1024 == 0)
- WATCHDOG_RESET();
+ schedule();
}
for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
break;
}
if (i % 1024 == 0)
- WATCHDOG_RESET();
+ schedule();
}
return ret;
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = 1 << (i % 32);
if (i % 1024 == 0)
- WATCHDOG_RESET();
+ schedule();
}
for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
break;
}
if (i % 1024 == 0)
- WATCHDOG_RESET();
+ schedule();
}
return ret;
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = i;
if (i % 1024 == 0)
- WATCHDOG_RESET();
+ schedule();
}
for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
break;
}
if (i % 1024 == 0)
- WATCHDOG_RESET();
+ schedule();
}
return ret;
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = ~i;
if (i % 1024 == 0)
- WATCHDOG_RESET();
+ schedule();
}
for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
break;
}
if (i % 1024 == 0)
- WATCHDOG_RESET();
+ schedule();
}
return ret;
int ret = 0;
ret = memory_post_dataline((unsigned long long *)start);
- WATCHDOG_RESET();
+ schedule();
if (!ret)
ret = memory_post_addrline((ulong *)start, (ulong *)start,
size);
- WATCHDOG_RESET();
+ schedule();
if (!ret)
ret = memory_post_addrline((ulong *)(start+size-8),
(ulong *)start, size);
- WATCHDOG_RESET();
+ schedule();
return ret;
}
int ret = 0;
ret = memory_post_test1(start, size, 0x00000000);
- WATCHDOG_RESET();
+ schedule();
if (!ret)
ret = memory_post_test1(start, size, 0xffffffff);
- WATCHDOG_RESET();
+ schedule();
if (!ret)
ret = memory_post_test1(start, size, 0x55555555);
- WATCHDOG_RESET();
+ schedule();
if (!ret)
ret = memory_post_test1(start, size, 0xaaaaaaaa);
- WATCHDOG_RESET();
+ schedule();
if (!ret)
ret = memory_post_test2(start, size);
- WATCHDOG_RESET();
+ schedule();
if (!ret)
ret = memory_post_test3(start, size);
- WATCHDOG_RESET();
+ schedule();
if (!ret)
ret = memory_post_test4(start, size);
- WATCHDOG_RESET();
+ schedule();
return ret;
}
int ic = icache_status();
int ret = 0;
- WATCHDOG_RESET();
+ schedule();
if (ic)
icache_disable();
ret = cpu_post_test_two ();
if (ret == 0)
ret = cpu_post_test_twox ();
- WATCHDOG_RESET();
+ schedule();
if (ret == 0)
ret = cpu_post_test_three ();
if (ret == 0)
ret = cpu_post_test_threei ();
if (ret == 0)
ret = cpu_post_test_andi ();
- WATCHDOG_RESET();
+ schedule();
if (ret == 0)
ret = cpu_post_test_srawi ();
if (ret == 0)
ret = cpu_post_test_rlwinm ();
if (ret == 0)
ret = cpu_post_test_rlwimi ();
- WATCHDOG_RESET();
+ schedule();
if (ret == 0)
ret = cpu_post_test_store ();
if (ret == 0)
ret = cpu_post_test_cr ();
if (ret == 0)
ret = cpu_post_test_b ();
- WATCHDOG_RESET();
+ schedule();
if (ret == 0)
ret = cpu_post_test_multi ();
- WATCHDOG_RESET();
+ schedule();
if (ret == 0)
ret = cpu_post_test_string ();
if (ret == 0)
ret = cpu_post_test_complex ();
- WATCHDOG_RESET();
+ schedule();
if (ic)
icache_enable();
- WATCHDOG_RESET();
+ schedule();
return ret;
}
int ret = 0;
- WATCHDOG_RESET ();
+ schedule();
if (!fpu)
fpu_enable ();
if (!fpu)
fpu_disable ();
- WATCHDOG_RESET ();
+ schedule();
return ret;
}
{
if ((flags & test_flags & POST_ALWAYS) &&
(flags & test_flags & POST_MEM)) {
- WATCHDOG_RESET();
+ schedule();
if (!(flags & POST_REBOOT)) {
if ((test_flags & POST_REBOOT) &&
}
if (i < post_list_size) {
- WATCHDOG_RESET();
+ schedule();
return post_run_single(post_list + i,
test_flags[i],
flags, i);
NULL));
/* Execute all registered cyclic functions */
- WATCHDOG_RESET();
+ schedule();
ut_asserteq(true, cyclic_active);
return 0;
*/
#include <common.h>
+#include <cyclic.h>
#include <dm.h>
#include <wdt.h>
#include <asm/gpio.h>
/* Neither device should be "started", so watchdog_reset() should be a no-op. */
reset_count = state->wdt.reset_count;
val = sandbox_gpio_get_value(gpio, offset);
- watchdog_reset();
+ cyclic_run();
ut_asserteq(reset_count, state->wdt.reset_count);
ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
/* Make sure both devices have just been pinged. */
timer_test_add_offset(100);
- watchdog_reset();
+ cyclic_run();
reset_count = state->wdt.reset_count;
val = sandbox_gpio_get_value(gpio, offset);
/* The gpio watchdog should be pinged, the sandbox one not. */
timer_test_add_offset(30);
- watchdog_reset();
+ cyclic_run();
ut_asserteq(reset_count, state->wdt.reset_count);
ut_asserteq(!val, sandbox_gpio_get_value(gpio, offset));
/* After another ~30ms, both devices should get pinged. */
timer_test_add_offset(30);
- watchdog_reset();
+ cyclic_run();
ut_asserteq(reset_count + 1, state->wdt.reset_count);
ut_asserteq(val, sandbox_gpio_get_value(gpio, offset));
projects / u-boot.git / commitdiff