arm: mach-k3: am62a7: Enable QoS for DSS

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to 8.

The C7x and VPAC have been overwhelming the DSS's access to the DDR
(when it was accessing via the Non Real-Time (NRT) Queue), primarily
because their functional frequencies, and hence DDR accesses, were
significantly higher than that of DSS. This led the display to flicker
when certain edgeAI models were being run.

With the DSS traffic serviced from the RT queue, the flickering issue
has been found to be mitigated.

The am62a qos files are auto generated from the k3 resource partitioning
tool.

Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
more information about the QoS, and section-14.1, "System Interconnect
Registers", provides the register descriptions.

[1] AM62A Tech Ref Manual: https://www.ti.com/lit/pdf/spruj16

Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>

diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c
index a89a9b4ae3a04e1398cc4814bb0471ebc66d0e78..1f51b0408969605b30ec6cbeb6045c5b501f1199 100644 (file)
--- a/arch/arm/mach-k3/am62a7_init.c
+++ b/arch/arm/mach-k3/am62a7_init.c
@@ -65,6 +65,20 @@ static void ctrl_mmr_unlock(void)
        mmr_unlock(PADCFG_MMR1_BASE, 1);
 }
 
+#if (IS_ENABLED(CONFIG_CPU_V7R))
+static void setup_qos(void)
+{
+       u32 i;
+
+       for (i = 0; i < am62a_qos_count; i++)
+               writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg);
+}
+#else
+static void setup_qos(void)
+{
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
        struct udevice *dev;
@@ -158,6 +172,8 @@ void board_init_f(ulong dummy)
                panic("DRAM init failed: %d\n", ret);
 #endif
 
+       setup_qos();
+
        printf("am62a_init: %s done\n", __func__);
 }
 

diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile
index c58e52df1fa2733cb2f130e0b6fc1845472b5377..02a941805e9a52a747e93df0a72a60b8b9c76a6f 100644 (file)
--- a/arch/arm/mach-k3/am62ax/Makefile
+++ b/arch/arm/mach-k3/am62ax/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += am62a_qos_data.o

diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/am62ax/am62a_qos_data.c
new file mode 100644 (file)
index 0000000..01b76f7
--- /dev/null
+++ b/arch/arm/mach-k3/am62ax/am62a_qos_data.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62a Quality of Service (QoS) Configuration Data
+ * Auto generated from K3 Resource Partitioning tool
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include "common.h"
+
+struct k3_qos_data am62a_qos_data[] = {
+       /* modules_qosConfig0 - 1 endpoints, 4 channels */
+       {
+               .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
+               .val = ORDERID_8,
+       },
+       {
+               .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1,
+               .val = ORDERID_8,
+       },
+       {
+               .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2,
+               .val = ORDERID_8,
+       },
+       {
+               .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3,
+               .val = ORDERID_8,
+       },
+
+       /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+        * remap registers. orderID x is remapped to orderID x again
+        * This is to ensure orderID from MAP register is unchanged
+        */
+
+       /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */
+       {
+               .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0,
+               .val = 0x76543210,
+       },
+       {
+               .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4,
+               .val = 0xfedcba98,
+       },
+};
+
+uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]);

diff --git a/arch/arm/mach-k3/include/mach/am62a_qos.h b/arch/arm/mach-k3/include/mach/am62a_qos.h
new file mode 100644 (file)
index 0000000..c74d69a
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am62a_qos.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define QOS_0  (0 << 0)
+#define QOS_1  (1 << 0)
+#define QOS_2  (2 << 0)
+#define QOS_3  (3 << 0)
+#define QOS_4  (4 << 0)
+#define QOS_5  (5 << 0)
+#define QOS_6  (6 << 0)
+#define QOS_7  (7 << 0)
+
+#define ORDERID_0      (0 << 4)
+#define ORDERID_1      (1 << 4)
+#define ORDERID_2      (2 << 4)
+#define ORDERID_3      (3 << 4)
+#define ORDERID_4      (4 << 4)
+#define ORDERID_5      (5 << 4)
+#define ORDERID_6      (6 << 4)
+#define ORDERID_7      (7 << 4)
+#define ORDERID_8      (8 << 4)
+#define ORDERID_9      (9 << 4)
+#define ORDERID_10     (10 << 4)
+#define ORDERID_11     (11 << 4)
+#define ORDERID_12     (12 << 4)
+#define ORDERID_13     (13 << 4)
+#define ORDERID_14     (14 << 4)
+#define ORDERID_15     (15 << 4)
+
+#define ASEL_0 (0 << 8)
+#define ASEL_1 (1 << 8)
+#define ASEL_2 (2 << 8)
+#define ASEL_3 (3 << 8)
+#define ASEL_4 (4 << 8)
+#define ASEL_5 (5 << 8)
+#define ASEL_6 (6 << 8)
+#define ASEL_7 (7 << 8)
+#define ASEL_8 (8 << 8)
+#define ASEL_9 (9 << 8)
+#define ASEL_10        (10 << 8)
+#define ASEL_11        (11 << 8)
+#define ASEL_12        (12 << 8)
+#define ASEL_13        (13 << 8)
+#define ASEL_14        (14 << 8)
+#define ASEL_15        (15 << 8)
+
+#define EPRIORITY_0    (0 << 12)
+#define EPRIORITY_1    (1 << 12)
+#define EPRIORITY_2    (2 << 12)
+#define EPRIORITY_3    (3 << 12)
+#define EPRIORITY_4    (4 << 12)
+#define EPRIORITY_5    (5 << 12)
+#define EPRIORITY_6    (6 << 12)
+#define EPRIORITY_7    (7 << 12)
+
+#define VIRTID_0       (0 << 16)
+#define VIRTID_1       (1 << 16)
+#define VIRTID_2       (2 << 16)
+#define VIRTID_3       (3 << 16)
+#define VIRTID_4       (4 << 16)
+#define VIRTID_5       (5 << 16)
+#define VIRTID_6       (6 << 16)
+#define VIRTID_7       (7 << 16)
+#define VIRTID_8       (8 << 16)
+#define VIRTID_9       (9 << 16)
+#define VIRTID_10      (10 << 16)
+#define VIRTID_11      (11 << 16)
+#define VIRTID_12      (12 << 16)
+#define VIRTID_13      (13 << 16)
+#define VIRTID_14      (14 << 16)
+#define VIRTID_15      (15 << 16)
+
+#define ATYPE_0        (0 << 28)
+#define ATYPE_1        (1 << 28)
+#define ATYPE_2        (2 << 28)
+#define ATYPE_3        (3 << 28)
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST     0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST     0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST     0x45D14800
+#define PULSAR_ULS_MCU_0_CPU0_RMST     0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST     0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST     0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R   0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W   0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW      0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR      0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM       0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM       0x45D22400
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD   0x45D22800
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR   0x45D22C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR   0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D23C00
+#define USB2SS_16FFC_MAIN_0_MSTW0      0x45D24000
+#define USB2SS_16FFC_MAIN_0_MSTR0      0x45D24400
+#define USB2SS_16FFC_MAIN_1_MSTR0      0x45D24800
+#define USB2SS_16FFC_MAIN_1_MSTW0      0x45D24C00
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA     0x45D25000
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA     0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W       0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R       0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC    0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC    0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC    0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC    0x45D27400
+#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC       0x45D27800
+#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST     0x45D28000

diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 9faf1d6ff064b5028004b8888f80b989c653bcb4..65742c4b7c8c7b5a478d740b87a18976f39d7b39 100644 (file)
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -30,6 +30,7 @@
 
 #ifdef CONFIG_SOC_K3_AM62A7
 #include "am62a_hardware.h"
+#include "am62a_qos.h"
 #endif
 
 /* Assuming these addresses and definitions stay common across K3 devices */
@@ -96,4 +97,12 @@ struct rom_extended_boot_data {
        u32 num_components;
 };
 
+struct k3_qos_data {
+       u32 reg;
+       u32 val;
+};
+
+extern struct k3_qos_data am62a_qos_data[];
+extern u32 am62a_qos_count;
+
 #endif /* _ASM_ARCH_HARDWARE_H_ */