ids8247: Remove legacy NAND defines

because legacy NAND support is deprecated converting to current
NAND interface. !This just compile, because I have no more the
hardware to test it.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c
index 68b70703f07772b9454e3b499fac92601fdb05f7..79fe9da5baf64677e7f8cac31709a63d5d275424 100644 (file)
--- a/board/ids8247/ids8247.c
+++ b/board/ids8247/ids8247.c
@@ -304,21 +304,97 @@ phys_size_t initdram (int board_type)
 int misc_init_r (void)
 {
        gd->bd->bi_flashstart = 0xff800000;
+       return 0;
 }
 
 #if defined(CONFIG_CMD_NAND)
-extern ulong
-nand_probe (ulong physadr);
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+#include <asm/io.h>
+
+static u8 hwctl;
+
+static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+       struct nand_chip *this = mtd->priv;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               if ( ctrl & NAND_CLE ) {
+                       hwctl |= 0x1;
+                       writeb(0x00, (this->IO_ADDR_W + 0x0a));
+               } else {
+                       hwctl &= ~0x1;
+                       writeb(0x00, (this->IO_ADDR_W + 0x08));
+               }
+               if ( ctrl & NAND_ALE ) {
+                       hwctl |= 0x2;
+                       writeb(0x00, (this->IO_ADDR_W + 0x09));
+               } else {
+                       hwctl &= ~0x2;
+                       writeb(0x00, (this->IO_ADDR_W + 0x08));
+               }
+               if ( (ctrl & NAND_NCE) != NAND_NCE)
+                       writeb(0x00, (this->IO_ADDR_W + 0x0c));
+               else
+                       writeb(0x00, (this->IO_ADDR_W + 0x08));
+       }
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
+
+}
 
-void
-nand_init (void)
+static u_char ids_nand_read_byte(struct mtd_info *mtd)
 {
-       ulong totlen = 0;
+       struct nand_chip *this = mtd->priv;
 
-       debug ("Probing at 0x%.8x\n", CONFIG_SYS_NAND0_BASE);
-       totlen += nand_probe (CONFIG_SYS_NAND0_BASE);
+       return readb(this->IO_ADDR_R);
+}
+
+static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+       struct nand_chip *nand = mtd->priv;
+       int i;
+
+       for (i = 0; i < len; i++) {
+               if (hwctl & 0x1)
+                       writeb(buf[i], (nand->IO_ADDR_W + 0x02));
+               else if (hwctl & 0x2)
+                       writeb(buf[i], (nand->IO_ADDR_W + 0x01));
+               else
+                       writeb(buf[i], nand->IO_ADDR_W);
+       }
+}
 
-       printf ("%4lu MB\n", totlen >>20);
+static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+       struct nand_chip *this = mtd->priv;
+       int i;
+
+       for (i = 0; i < len; i++) {
+               buf[i] = readb(this->IO_ADDR_R);
+       }
+}
+
+static int ids_nand_dev_ready(struct mtd_info *mtd)
+{
+       /* constant delay (see also tR in the datasheet) */
+       udelay(12);
+       return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+       nand->ecc.mode = NAND_ECC_SOFT;
+
+       /* Reference hardware control function */
+       nand->cmd_ctrl  = ids_nand_hwctrl;
+       nand->read_byte  = ids_nand_read_byte;
+       nand->write_buf  = ids_nand_write_buf;
+       nand->read_buf   = ids_nand_read_buf;
+       nand->dev_ready  = ids_nand_dev_ready;
+       nand->chip_delay = 12;
+
+       return 0;
 }
 
 #endif /* CONFIG_CMD_NAND */

diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index fbcbddb408de636ac82cfd69441698d0ceed8e33..51e012cc467d070a5b764787e4585eb7ec7e8f5e 100644 (file)
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -262,63 +262,8 @@
  */
 #if defined(CONFIG_CMD_NAND)
 
-#define CONFIG_NAND_LEGACY
 #define CONFIG_SYS_NAND0_BASE 0xE1000000
-
 #define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
-#define SECTORSIZE 512
-#define NAND_NO_RB
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN     0x00
-#define NAND_MAX_FLOORS 1
-
-#define NAND_DISABLE_CE(nand) do \
-{ \
-       *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
-} while(0)
-
-#define NAND_ENABLE_CE(nand) do \
-{ \
-       *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
-} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) do \
-{ \
-       *(((volatile __u8 *)nandptr) + 0x8) = 0; \
-} while(0)
-
-#define NAND_CTL_SETALE(nandptr) do \
-{ \
-       *(((volatile __u8 *)nandptr) + 0x9) = 0; \
-} while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) do \
-{ \
-       *(((volatile __u8 *)nandptr) + 0x8) = 0; \
-} while(0)
-
-#define NAND_CTL_SETCLE(nandptr) do \
-{ \
-       *(((volatile __u8 *)nandptr) + 0xa) = 0; \
-} while(0)
-
-#ifdef NAND_NO_RB
-/* constant delay (see also tR in the datasheet) */
-#define NAND_WAIT_READY(nand) do { \
-       udelay(12); \
-} while (0)
-#else
-/* use the R/B pin */
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
 
 #endif /* CONFIG_CMD_NAND */