#define __ARC_BCR_H
#ifndef __ASSEMBLY__
-#include <config.h>
-
union bcr_di_cache {
struct {
#ifdef CONFIG_CPU_BIG_ENDIAN
#define _ASM_ARC_ARCREGS_H
#include <asm/cache.h>
-#include <config.h>
/*
* ARC architecture has additional address space - auxiliary registers.
#ifndef __ASM_ARC_CACHE_H
#define __ASM_ARC_CACHE_H
-#include <config.h>
-
/*
* As of today we may handle any L1 cache line length right in software.
* For that essentially cache line length is a variable not constant.
* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
*/
+#include <config.h>
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
writel(0x1, (void *)CRM_SWRESET);
}
+/*
+ * Ethernet configuration
+ */
+#define ETH0_BASE_ADDRESS 0xFE100000
int board_eth_init(struct bd_info *bis)
{
if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0)
*/
#define CFG_SYS_NS16550_CLK 166666666
-/*
- * Even though the board houses Realtek RTL8211E PHY
- * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly.
- * In particular "parse_status" reports link is down.
- *
- * Until Realtek PHY driver is fixed fall back to generic PHY driver
- * which implements all required functionality and behaves much more stable.
- *
- *
- */
-
-/*
- * Ethernet configuration
- */
-#define ETH0_BASE_ADDRESS 0xFE100000
-#define ETH1_BASE_ADDRESS 0xFE110000
-
-/*
- * Console configuration
- */
-
#endif /* _CONFIG_TB100_H_ */