s3c4510b: move specific code to soc directory

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

diff --git a/Makefile b/Makefile
index 1cce381f611a4257ffc3c8229e3771d2a63b7142..a6dadf65ba57a971f159856c0e77173f9d14852f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2943,7 +2943,7 @@ modnet50_config : unconfig
        @$(MKCONFIG) $(@:_config=) arm arm720t modnet50
 
 evb4510_config :       unconfig
-       @$(MKCONFIG) $(@:_config=) arm arm720t evb4510
+       @$(MKCONFIG) $(@:_config=) arm arm720t evb4510 NULL s3c4510b
 
 lpc2292sodimm_config:  unconfig
        @$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm NULL lpc2292

diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 5ac8f59ab3caf2f1b551fc919b0ff64d3e814d52..8166982e6a7d0ab0892247c2dbb77a24930a4509 100644 (file)
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -188,71 +188,9 @@ int dcache_status (void)
 {
        return (read_p15_c1 () & C1_IDC) != 0;
 }
-
-#elif defined(CONFIG_S3C4510B)
-
-void icache_enable (void)
-{
-       s32 i;
-
-       /* disable all cache bits */
-       CLR_REG( REG_SYSCFG, 0x3F);
-
-       /* 8KB cache, write enable */
-       SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
-
-       /* clear TAG RAM bits */
-       for ( i = 0; i < 256; i++)
-         PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
-
-       /* clear SET0 RAM */
-       for(i=0; i < 1024; i++)
-         PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
-
-       /* clear SET1 RAM */
-       for(i=0; i < 1024; i++)
-         PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
-
-       /* enable cache */
-       SET_REG( REG_SYSCFG, CACHE_ENABLE);
-
-}
-
-void icache_disable (void)
-{
-       /* disable all cache bits */
-       CLR_REG( REG_SYSCFG, 0x3F);
-}
-
-int icache_status (void)
-{
-       return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
-}
-
-void dcache_enable (void)
-{
-       /* we don't have seperate instruction/data caches */
-       icache_enable();
-}
-
-void dcache_disable (void)
-{
-       /* we don't have seperate instruction/data caches */
-       icache_disable();
-}
-
-int dcache_status (void)
-{
-       /* we don't have seperate instruction/data caches */
-       return icache_status();
-}
-
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
        /* No specific cache setup for IntegratorAP/CM720T as yet */
        void icache_enable (void)
        {
        }
-#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
-#else
-#error No icache/dcache enable/disable functions defined for this CPU type
 #endif

diff --git a/cpu/arm720t/s3c4510b/Makefile b/cpu/arm720t/s3c4510b/Makefile
new file mode 100644 (file)
index 0000000..c9520b6
--- /dev/null
+++ b/cpu/arm720t/s3c4510b/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(SOC).a
+
+COBJS-y        += cache.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+

diff --git a/cpu/arm720t/s3c4510b/cache.c b/cpu/arm720t/s3c4510b/cache.c
new file mode 100644 (file)
index 0000000..104d287
--- /dev/null
+++ b/cpu/arm720t/s3c4510b/cache.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+void icache_enable (void)
+{
+       s32 i;
+
+       /* disable all cache bits */
+       CLR_REG( REG_SYSCFG, 0x3F);
+
+       /* 8KB cache, write enable */
+       SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
+
+       /* clear TAG RAM bits */
+       for ( i = 0; i < 256; i++)
+         PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
+
+       /* clear SET0 RAM */
+       for(i=0; i < 1024; i++)
+         PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
+
+       /* clear SET1 RAM */
+       for(i=0; i < 1024; i++)
+         PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
+
+       /* enable cache */
+       SET_REG( REG_SYSCFG, CACHE_ENABLE);
+
+}
+
+void icache_disable (void)
+{
+       /* disable all cache bits */
+       CLR_REG( REG_SYSCFG, 0x3F);
+}
+
+int icache_status (void)
+{
+       return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
+}
+
+void dcache_enable (void)
+{
+       /* we don't have seperate instruction/data caches */
+       icache_enable();
+}
+
+void dcache_disable (void)
+{
+       /* we don't have seperate instruction/data caches */
+       icache_disable();
+}
+
+int dcache_status (void)
+{
+       /* we don't have seperate instruction/data caches */
+       return icache_status();
+}

diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h
index 3056ca7f673ad919f170e6083eb5026122853e25..ec053c9912d7f614cbc7ff50e87014b536d37f48 100644 (file)
--- a/include/asm-arm/arch-arm720t/hardware.h
+++ b/include/asm-arm/arch-arm720t/hardware.h
@@ -24,9 +24,7 @@
  * MA 02111-1307 USA
  */
 
-#if defined(CONFIG_S3C4510B)
-#include <asm-arm/arch-arm720t/s3c4510b.h>
-#elif defined(CONFIG_NETARM)
+#if defined(CONFIG_NETARM)
 #include <asm-arm/arch-arm720t/netarm_registers.h>
 #elif defined(CONFIG_IMPA7)
 /* include IMPA7 specific hardware file if there was one */

diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-s3c4510b/hardware.h
similarity index 100%
rename from include/asm-arm/arch-arm720t/s3c4510b.h
rename to include/asm-arm/arch-s3c4510b/hardware.h