ARM64: zynqmp: Wire up both USBs available on ZynqMP

The second USB wasn't enabled. This patch fixes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 0c5d9979316f2cd0a8f4fa0f2d3204ecb063f3c0..7b4b5ffd89f44051e6085bff6e94349597fef6e4 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -283,13 +283,20 @@ int checkboard(void)
 }
 
 #ifdef CONFIG_USB_DWC3
-static struct dwc3_device dwc3_device_data = {
+static struct dwc3_device dwc3_device_data0 = {
        .maximum_speed = USB_SPEED_HIGH,
        .base = ZYNQMP_USB0_XHCI_BASEADDR,
        .dr_mode = USB_DR_MODE_PERIPHERAL,
        .index = 0,
 };
 
+static struct dwc3_device dwc3_device_data1 = {
+       .maximum_speed = USB_SPEED_HIGH,
+       .base = ZYNQMP_USB1_XHCI_BASEADDR,
+       .dr_mode = USB_DR_MODE_PERIPHERAL,
+       .index = 1,
+};
+
 int usb_gadget_handle_interrupts(void)
 {
        dwc3_uboot_handle_interrupt(0);
@@ -298,7 +305,16 @@ int usb_gadget_handle_interrupts(void)
 
 int board_usb_init(int index, enum usb_init_type init)
 {
-       return dwc3_uboot_init(&dwc3_device_data);
+       debug("%s: index %x\n", __func__, index);
+
+       switch (index) {
+       case 0:
+               return dwc3_uboot_init(&dwc3_device_data0);
+       case 1:
+               return dwc3_uboot_init(&dwc3_device_data1);
+       };
+
+       return -1;
 }
 
 int board_usb_cleanup(int index, enum usb_init_type init)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index c43ea19807412e3fc2fc4496aee5a7b45006fdc3..ee8d1e0da0b811818528c3b8c93a490182df21ee 100644 (file)
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -108,7 +108,7 @@
 #define CONFIG_SYS_LOAD_ADDR           0x8000000
 
 #if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 #define CONFIG_USB_XHCI_ZYNQMP